Home
last modified time | relevance | path

Searched refs:uint32_t (Results 1 – 25 of 1646) sorted by relevance

12345678910>>...66

/hal_espressif-latest/components/soc/esp32s3/include/soc/
Dsystem_struct.h26 uint32_t control_core_1_runstall : 1;
27 uint32_t control_core_1_clkgate_en : 1;
28 uint32_t control_core_1_reseting : 1;
29 uint32_t reserved3 : 29;
31 uint32_t val;
33 uint32_t core_1_control_1;
36 uint32_t reserved0 : 6;
37 uint32_t clk_en_assist_debug : 1;
38 uint32_t clk_en_dedicated_gpio : 1;
39 uint32_t reserved8 : 24;
[all …]
Dinterrupt_core1_struct.h22 uint32_t reserved_0;
23 uint32_t reserved_4;
24 uint32_t reserved_8;
25 uint32_t reserved_c;
26 uint32_t reserved_10;
27 uint32_t reserved_14;
28 uint32_t reserved_18;
29 uint32_t reserved_1c;
30 uint32_t reserved_20;
31 uint32_t reserved_24;
[all …]
Dsensitive_struct.h26 uint32_t cache_dataarray_connect_lock : 1;
27 uint32_t reserved1 : 31;
29 uint32_t val;
33 uint32_t cache_dataarray_connect_flatten: 8;
34 uint32_t reserved8 : 24;
36 uint32_t val;
40 uint32_t apb_peripheral_access_lock : 1;
41 uint32_t reserved1 : 31;
43 uint32_t val;
47 uint32_t apb_peripheral_access_split_burst: 1;
[all …]
Dinterrupt_core0_struct.h24 uint32_t core0_mac_intr_map: 5;
25 uint32_t reserved5: 27;
27 uint32_t val;
31 uint32_t core0_mac_nmi_map: 5;
32 uint32_t reserved5: 27;
34 uint32_t val;
38 uint32_t core0_pwr_intr_map: 5;
39 uint32_t reserved5: 27;
41 uint32_t val;
45 uint32_t core0_bb_int_map: 5;
[all …]
Drtc_cntl_struct.h19 …uint32_t sw_stall_appcpu_c0 : 2; /*{reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appc…
20 …uint32_t sw_stall_procpu_c0 : 2; /*{reg_sw_stall_procpu_c1[5:0], reg_sw_stall_proc…
21 uint32_t sw_appcpu_rst : 1; /*APP CPU SW reset*/
22 uint32_t sw_procpu_rst : 1; /*PRO CPU SW reset*/
23 uint32_t bb_i2c_force_pd : 1; /*BB_I2C force power down*/
24 uint32_t bb_i2c_force_pu : 1; /*BB_I2C force power up*/
25 uint32_t bbpll_i2c_force_pd : 1; /*BB_PLL _I2C force power down*/
26 uint32_t bbpll_i2c_force_pu : 1; /*BB_PLL_I2C force power up*/
27 uint32_t bbpll_force_pd : 1; /*BB_PLL force power down*/
28 uint32_t bbpll_force_pu : 1; /*BB_PLL force power up*/
[all …]
Dspi_mem_struct.h26 uint32_t reserved0 : 17; /*reserved*/
27 …uint32_t flash_pe : 1; /*In user mode, it is set to indicate that program…
28 …uint32_t usr : 1; /*User define command enable. An operation will b…
29 …uint32_t flash_hpm : 1; /*Drive Flash into high performance mode. The bit…
30 …uint32_t flash_res : 1; /*This bit combined with SPI_MEM_RESANDRES bit rel…
31 …uint32_t flash_dp : 1; /*Drive Flash into power down. An operation will …
32 …uint32_t flash_ce : 1; /*Chip erase enable. Chip erase operation will be …
33 …uint32_t flash_be : 1; /*Block erase enable(32KB) . Block erase operatio…
34 …uint32_t flash_se : 1; /*Sector erase enable(4KB). Sector erase operation…
35 …uint32_t flash_pp : 1; /*Page program enable(1 byte ~64 bytes data to be …
[all …]
Dextmem_struct.h26 …uint32_t dcache_enable : 1; /*The bit is used to activate the data cache. 0: d…
27 uint32_t reserved1 : 1; /*Reserved*/
28 …uint32_t dcache_size_mode : 1; /*The bit is used to configure cache memory size.0…
29 …uint32_t dcache_blocksize_mode : 2; /*The bit is used to configure cache block size.0:…
30 uint32_t reserved5 : 27;
32 uint32_t val;
36 …uint32_t dcache_shut_core0_bus : 1; /*The bit is used to disable core0 dbus, 0: enable…
37 …uint32_t dcache_shut_core1_bus : 1; /*The bit is used to disable core1 dbus, 0: enable…
38 uint32_t reserved2 : 30;
40 uint32_t val;
[all …]
Dusb_wrap_struct.h34 uint32_t srp_sessend_override:1;
38 uint32_t srp_sessend_value:1;
42 uint32_t phy_sel:1;
46 uint32_t dfifo_force_pd:1;
50 uint32_t dbnce_fltr_bypass:1;
54 uint32_t exchg_pins_override:1;
58 uint32_t exchg_pins:1;
62 uint32_t vrefh:2;
66 uint32_t vrefl:2;
70 uint32_t vref_override:1;
[all …]
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Dsystem_struct.h26 uint32_t reserved0 : 6; /*reserved*/
27 uint32_t reg_clk_en_assist_debug : 1; /*reg_clk_en_assist_debug*/
28 uint32_t reg_clk_en_dedicated_gpio : 1; /*reg_clk_en_dedicated_gpio*/
29 uint32_t reserved8 : 24; /*reserved*/
31 uint32_t val;
35 uint32_t reserved0 : 6; /*reserved*/
36 uint32_t reg_rst_en_assist_debug : 1; /*reg_rst_en_assist_debug*/
37 uint32_t reg_rst_en_dedicated_gpio : 1; /*reg_rst_en_dedicated_gpio*/
38 uint32_t reserved8 : 24; /*reserved*/
40 uint32_t val;
[all …]
Dsensitive_struct.h26 uint32_t reg_rom_table_lock : 1; /*rom_table_lock*/
27 uint32_t reserved1 : 31;
29 uint32_t val;
31 uint32_t rom_table;
34 uint32_t reg_privilege_mode_sel_lock : 1; /*privilege_mode_sel_lock*/
35 uint32_t reserved1 : 31;
37 uint32_t val;
41 uint32_t reg_privilege_mode_sel : 1; /*privilege_mode_sel*/
42 uint32_t reserved1 : 31;
44 uint32_t val;
[all …]
Drtc_cntl_struct.h16 …uint32_t sw_stall_appcpu_c0: 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcp…
17 …uint32_t sw_stall_procpu_c0: 2; /*{reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procp…
18 uint32_t sw_appcpu_rst: 1; /*APP CPU SW reset*/
19 uint32_t sw_procpu_rst: 1; /*PRO CPU SW reset*/
20 uint32_t bb_i2c_force_pd: 1; /*BB_I2C force power down*/
21 uint32_t bb_i2c_force_pu: 1; /*BB_I2C force power up*/
22 uint32_t bbpll_i2c_force_pd: 1; /*BB_PLL _I2C force power down*/
23 uint32_t bbpll_i2c_force_pu: 1; /*BB_PLL_I2C force power up*/
24 uint32_t bbpll_force_pd: 1; /*BB_PLL force power down*/
25 uint32_t bbpll_force_pu: 1; /*BB_PLL force power up*/
[all …]
Dapb_saradc_struct.h17 uint32_t start_force: 1;
18 uint32_t start: 1;
19 …uint32_t reserved2: 4; /*0: single mode 1: double mode 2: alternate m…
20 uint32_t sar_clk_gated: 1;
21 uint32_t sar_clk_div: 8; /*SAR clock divider*/
22 uint32_t sar_patt_len: 3; /*0 ~ 15 means length 1 ~ 16*/
23 uint32_t reserved18: 5;
24 …uint32_t sar_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC…
25 uint32_t reserved24: 3;
26 uint32_t xpd_sar_force: 2; /*force option to xpd sar blocks*/
[all …]
Dspi_mem_struct.h16 uint32_t mst_st: 4; /*The current status of SPI1 master FSM.*/
17 …uint32_t st: 4; /*The current status of SPI1 slave FSM: mspi_st. 0: id…
18 uint32_t reserved8: 9; /*reserved*/
19 …uint32_t flash_pe: 1; /*In user mode it is set to indicate that program/era…
20 …uint32_t usr: 1; /*User define command enable. An operation will be tr…
21 …uint32_t flash_hpm: 1; /*Drive Flash into high performance mode. The bit wil…
22 …uint32_t flash_res: 1; /*This bit combined with reg_resandres bit releases Fl…
23 …uint32_t flash_dp: 1; /*Drive Flash into power down. An operation will be t…
24 …uint32_t flash_ce: 1; /*Chip erase enable. Chip erase operation will be trig…
25 …uint32_t flash_be: 1; /*Block erase enable(32KB) . Block erase operation wi…
[all …]
/hal_espressif-latest/components/soc/esp32/include/soc/
Dslc_struct.h26 uint32_t slc0_tx_rst: 1;
27 uint32_t slc0_rx_rst: 1;
28 uint32_t ahbm_fifo_rst: 1;
29 uint32_t ahbm_rst: 1;
30 uint32_t slc0_tx_loop_test: 1;
31 uint32_t slc0_rx_loop_test: 1;
32 uint32_t slc0_rx_auto_wrback: 1;
33 uint32_t slc0_rx_no_restart_clr: 1;
34 uint32_t slc0_rxdscr_burst_en: 1;
35 uint32_t slc0_rxdata_burst_en: 1;
[all …]
Dhost_struct.h24 uint32_t reserved_0;
25 uint32_t reserved_4;
26 uint32_t reserved_8;
27 uint32_t reserved_c;
30 uint32_t reserved0: 24;
31 uint32_t func2_int: 1;
32 uint32_t reserved25: 7;
34 uint32_t val;
38 uint32_t func2_int_en: 1;
39 uint32_t reserved1: 31;
[all …]
Dspi_struct.h26 uint32_t reserved0: 16; /*reserved*/
27 …uint32_t flash_per: 1; /*program erase resume bit program erase suspend …
28 …uint32_t flash_pes: 1; /*program erase suspend bit program erase suspend…
29 …uint32_t usr: 1; /*User define command enable. An operation will b…
30 …uint32_t flash_hpm: 1; /*Drive Flash into high performance mode. The bit…
31 …uint32_t flash_res: 1; /*This bit combined with reg_resandres bit release…
32 …uint32_t flash_dp: 1; /*Drive Flash into power down. An operation will …
33 …uint32_t flash_ce: 1; /*Chip erase enable. Chip erase operation will be …
34 …uint32_t flash_be: 1; /*Block erase enable(32KB) . Block erase operatio…
35 …uint32_t flash_se: 1; /*Sector erase enable(4KB). Sector erase operation…
[all …]
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Dspi_struct.h17 …uint32_t conf_bitlen:23; /*Define the spi_clk cycles of SPI_CONF state. Can …
18 uint32_t reserved23: 1; /*reserved*/
19 …uint32_t usr: 1; /*User define command enable. An operation will be …
20 uint32_t reserved25: 7; /*reserved*/
22 uint32_t val;
24 …uint32_t addr; /*[31:8]:address to slave [7:0]:Reserved. C…
27 uint32_t reserved0: 2; /*reserved*/
28 …uint32_t ext_hold_en: 1; /*Set the bit to hold spi. The bit is combined with …
29 …uint32_t dummy_out: 1; /*In the dummy phase the signal level of spi is outp…
30 uint32_t reserved4: 1; /*reserved*/
[all …]
Dspi_mem_struct.h17 uint32_t reserved0: 17; /*reserved*/
18 …uint32_t flash_pe: 1; /*In user mode it is set to indicate that pro…
19 …uint32_t usr: 1; /*User define command enable. An operation wi…
20 …uint32_t flash_hpm: 1; /*Drive Flash into high performance mode. The…
21 …uint32_t flash_res: 1; /*This bit combined with reg_resandres bit rel…
22 …uint32_t flash_dp: 1; /*Drive Flash into power down. An operation w…
23 …uint32_t flash_ce: 1; /*Chip erase enable. Chip erase operation will…
24 …uint32_t flash_be: 1; /*Block erase enable(32KB) . Block erase oper…
25 …uint32_t flash_se: 1; /*Sector erase enable(4KB). Sector erase opera…
26 …uint32_t flash_pp: 1; /*Page program enable(1 byte ~256 bytes data t…
[all …]
Drtc_cntl_struct.h25 …uint32_t sw_stall_appcpu_c0: 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_…
26 …uint32_t sw_stall_procpu_c0: 2; /*{reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_…
27 uint32_t sw_appcpu_rst: 1; /*APP CPU SW reset*/
28 uint32_t sw_procpu_rst: 1; /*PRO CPU SW reset*/
29 uint32_t bb_i2c_force_pd: 1; /*BB_I2C force power down*/
30 uint32_t bb_i2c_force_pu: 1; /*BB_I2C force power up*/
31 uint32_t bbpll_i2c_force_pd: 1; /*BB_PLL _I2C force power down*/
32 uint32_t bbpll_i2c_force_pu: 1; /*BB_PLL_I2C force power up*/
33 uint32_t bbpll_force_pd: 1; /*BB_PLL force power down*/
34 uint32_t bbpll_force_pu: 1; /*BB_PLL force power up*/
[all …]
Dapb_saradc_struct.h17 uint32_t start_force: 1;
18 uint32_t start: 1;
19 uint32_t reserved2: 1;
20 … uint32_t work_mode: 2; /*0: single mode 1: double mode 2: alternate mode*/
21 … uint32_t sar_sel: 1; /*0: SAR1 1: SAR2 only work for single SAR mode*/
22 uint32_t sar_clk_gated: 1;
23 uint32_t sar_clk_div: 8; /*SAR clock divider*/
24 uint32_t sar1_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/
25 uint32_t sar2_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/
26 …uint32_t sar1_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC1 CTR…
[all …]
Dusb_wrap_struct.h33 uint32_t srp_sessend_override:1;
37 uint32_t srp_sessend_value:1;
41 uint32_t phy_sel:1;
45 uint32_t dfifo_force_pd:1;
49 uint32_t dbnce_fltr_bypass:1;
53 uint32_t exchg_pins_override:1;
57 uint32_t exchg_pins:1;
61 uint32_t vrefh:2;
65 uint32_t vrefl:2;
69 uint32_t vref_override:1;
[all …]
/hal_espressif-latest/components/soc/esp32c6/include/soc/
Dspi_mem_struct.h16 …uint32_t mst_st : 4; /*The current status of SPI0 master FSM: spi0_mst_…
17 …uint32_t slv_st : 4; /*The current status of SPI0 slave FSM: mspi_st. 0…
18 uint32_t reserved8 : 9; /*reserved*/
19 …uint32_t flash_pe : 1; /*In user mode, it is set to indicate that program…
20 …uint32_t usr : 1; /*SPI0 USR_CMD start bit, only used when SPI_MEM_A…
21 …uint32_t flash_hpm : 1; /*Drive Flash into high performance mode. The bit…
22 …uint32_t flash_res : 1; /*This bit combined with reg_resandres bit release…
23 …uint32_t flash_dp : 1; /*Drive Flash into power down. An operation will …
24 …uint32_t flash_ce : 1; /*Chip erase enable. Chip erase operation will be …
25 …uint32_t flash_be : 1; /*Block erase enable(32KB) . Block erase operatio…
[all …]
/hal_espressif-latest/components/soc/esp32h2/include/soc/
Dspi_mem_struct.h17 …uint32_t mst_st : 4; /*The current status of SPI0 master FSM: spi0_mst_…
18 …uint32_t slv_st : 4; /*The current status of SPI0 slave FSM: mspi_st. 0…
19 uint32_t reserved8 : 9; /*reserved*/
20 …uint32_t flash_pe : 1; /*In user mode, it is set to indicate that program…
21 …uint32_t usr : 1; /*SPI0 USR_CMD start bit, only used when SPI_MEM_A…
22 …uint32_t flash_hpm : 1; /*Drive Flash into high performance mode. The bit…
23 …uint32_t flash_res : 1; /*This bit combined with reg_resandres bit release…
24 …uint32_t flash_dp : 1; /*Drive Flash into power down. An operation will …
25 …uint32_t flash_ce : 1; /*Chip erase enable. Chip erase operation will be …
26 …uint32_t flash_be : 1; /*Block erase enable(32KB) . Block erase operatio…
[all …]
/hal_espressif-latest/components/soc/esp32c2/include/soc/
Drtc_cntl_struct.h17 uint32_t reserved0 : 2; /*Reserved*/
18 …uint32_t sw_stall_procpu_c0 : 2; /*{reg_sw_stall_procpu_c1[5:0], reg_sw_stall_proc…
19 uint32_t reserved4 : 1; /*Reserved*/
20 uint32_t sw_procpu_rst : 1; /*PRO CPU SW reset*/
21 uint32_t bb_i2c_force_pd : 1; /*BB_I2C force power down*/
22 uint32_t bb_i2c_force_pu : 1; /*BB_I2C force power up*/
23 uint32_t bbpll_i2c_force_pd : 1; /*BB_PLL _I2C force power down*/
24 uint32_t bbpll_i2c_force_pu : 1; /*BB_PLL_I2C force power up*/
25 uint32_t bbpll_force_pd : 1; /*BB_PLL force power down*/
26 uint32_t bbpll_force_pu : 1; /*BB_PLL force power up*/
[all …]
Dspi_mem_struct.h17 … uint32_t mst_st : 4; /*The current status of SPI1 master FSM.*/
18 …uint32_t slv_st : 4; /*The current status of SPI1 slave FSM: mspi_st. 0…
19 uint32_t reserved8 : 9; /*reserved*/
20 …uint32_t flash_pe : 1; /*In user mode, it is set to indicate that program…
21 …uint32_t usr : 1; /*User define command enable. An operation will b…
22 …uint32_t flash_hpm : 1; /*Drive Flash into high performance mode. The bit…
23 …uint32_t flash_res : 1; /*This bit combined with reg_resandres bit release…
24 …uint32_t flash_dp : 1; /*Drive Flash into power down. An operation will …
25 …uint32_t flash_ce : 1; /*Chip erase enable. Chip erase operation will be …
26 …uint32_t flash_be : 1; /*Block erase enable(32KB) . Block erase operatio…
[all …]

12345678910>>...66