Searched refs:tx_conf (Results 1 – 10 of 10) sorted by relevance
147 hw->tx_conf.tx_slave_mod = slave_en; in i2s_ll_tx_set_slave_mod()168 hw->tx_conf.tx_reset = 1; in i2s_ll_tx_reset()169 hw->tx_conf.tx_reset = 0; in i2s_ll_tx_reset()190 hw->tx_conf.tx_fifo_reset = 1; in i2s_ll_tx_reset_fifo()191 hw->tx_conf.tx_fifo_reset = 0; in i2s_ll_tx_reset_fifo()265 hw->tx_conf.tx_bck_div_num = val - 1; in i2s_ll_tx_set_bck_div_num()392 hw->tx_conf.tx_update = 1; in i2s_ll_tx_start()393 while (hw->tx_conf.tx_update); in i2s_ll_tx_start()394 hw->tx_conf.tx_start = 1; in i2s_ll_tx_start()417 hw->tx_conf.tx_start = 0; in i2s_ll_tx_stop()[all …]
138 hw->tx_conf.tx_slave_mod = slave_en; in i2s_ll_tx_set_slave_mod()159 hw->tx_conf.tx_reset = 1; in i2s_ll_tx_reset()160 hw->tx_conf.tx_reset = 0; in i2s_ll_tx_reset()181 hw->tx_conf.tx_fifo_reset = 1; in i2s_ll_tx_reset_fifo()182 hw->tx_conf.tx_fifo_reset = 0; in i2s_ll_tx_reset_fifo()373 hw->tx_conf.tx_update = 1; in i2s_ll_tx_start()374 while (hw->tx_conf.tx_update); in i2s_ll_tx_start()375 hw->tx_conf.tx_start = 1; in i2s_ll_tx_start()398 hw->tx_conf.tx_start = 0; in i2s_ll_tx_stop()642 hw->tx_conf.tx_chan_mod = mod; in i2s_ll_tx_set_pdm_chan_mod()[all …]
146 hw->tx_conf.tx_slave_mod = slave_en; in i2s_ll_tx_set_slave_mod()167 hw->tx_conf.tx_reset = 1; in i2s_ll_tx_reset()168 hw->tx_conf.tx_reset = 0; in i2s_ll_tx_reset()189 hw->tx_conf.tx_fifo_reset = 1; in i2s_ll_tx_reset_fifo()190 hw->tx_conf.tx_fifo_reset = 0; in i2s_ll_tx_reset_fifo()385 hw->tx_conf.tx_update = 1; in i2s_ll_tx_start()386 while (hw->tx_conf.tx_update); in i2s_ll_tx_start()387 hw->tx_conf.tx_start = 1; in i2s_ll_tx_start()410 hw->tx_conf.tx_start = 0; in i2s_ll_tx_stop()654 hw->tx_conf.tx_chan_mod = mod; in i2s_ll_tx_set_pdm_chan_mod()[all …]
137 hw->tx_conf.tx_slave_mod = slave_en; in i2s_ll_tx_set_slave_mod()158 hw->tx_conf.tx_reset = 1; in i2s_ll_tx_reset()159 hw->tx_conf.tx_reset = 0; in i2s_ll_tx_reset()180 hw->tx_conf.tx_fifo_reset = 1; in i2s_ll_tx_reset_fifo()181 hw->tx_conf.tx_fifo_reset = 0; in i2s_ll_tx_reset_fifo()372 hw->tx_conf.tx_update = 1; in i2s_ll_tx_start()373 while (hw->tx_conf.tx_update); in i2s_ll_tx_start()374 hw->tx_conf.tx_start = 1; in i2s_ll_tx_start()397 hw->tx_conf.tx_start = 0; in i2s_ll_tx_stop()641 hw->tx_conf.tx_chan_mod = mod; in i2s_ll_tx_set_pdm_chan_mod()[all …]
174 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->tx_conf[channel], div_cnt, div); in rmt_ll_tx_set_channel_clock_div()186 dev->tx_conf[channel].mem_rd_rst = 1; in rmt_ll_tx_reset_pointer()187 dev->tx_conf[channel].mem_rd_rst = 0; in rmt_ll_tx_reset_pointer()188 dev->tx_conf[channel].mem_rst = 1; in rmt_ll_tx_reset_pointer()189 dev->tx_conf[channel].mem_rst = 0; in rmt_ll_tx_reset_pointer()202 dev->tx_conf[channel].conf_update = 1; in rmt_ll_tx_start()203 dev->tx_conf[channel].tx_start = 1; in rmt_ll_tx_start()215 dev->tx_conf[channel].tx_stop = 1; in rmt_ll_tx_stop()217 dev->tx_conf[channel].conf_update = 1; in rmt_ll_tx_stop()229 dev->tx_conf[channel].mem_size = block_num; in rmt_ll_tx_set_mem_blocks()[all …]
37 } tx_conf[2]; member
112 } tx_conf; member
114 } tx_conf; member
993 volatile i2s_tx_conf_reg_t tx_conf; member
991 volatile i2s_tx_conf_reg_t tx_conf; member
