Searched refs:rx_tdm_ctrl (Results 1 – 8 of 8) sorted by relevance
533 hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = total_num - 1; in i2s_ll_rx_set_chan_num()558 uint32_t tdm_ctrl = hw->rx_tdm_ctrl.val; in i2s_ll_rx_set_active_chan_mask()561 hw->rx_tdm_ctrl.val = tdm_ctrl; in i2s_ll_rx_set_active_chan_mask()603 hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = 1; // rx_tdm_tot_chan_num = 2 slots - 1 = 1 in i2s_ll_rx_select_std_slot()
545 hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = total_num - 1; in i2s_ll_rx_set_chan_num()570 uint32_t tdm_ctrl = hw->rx_tdm_ctrl.val; in i2s_ll_rx_set_active_chan_mask()573 hw->rx_tdm_ctrl.val = tdm_ctrl; in i2s_ll_rx_set_active_chan_mask()615 hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = 1; // rx_tdm_tot_chan_num = 2 slots - 1 = 1 in i2s_ll_rx_select_std_slot()
532 hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = total_num - 1; in i2s_ll_rx_set_chan_num()557 uint32_t tdm_ctrl = hw->rx_tdm_ctrl.val; in i2s_ll_rx_set_active_chan_mask()560 hw->rx_tdm_ctrl.val = tdm_ctrl; in i2s_ll_rx_set_active_chan_mask()602 hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = 1; // rx_tdm_tot_chan_num = 2 slots - 1 = 1 in i2s_ll_rx_select_std_slot()
552 hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = total_num - 1; in i2s_ll_rx_set_chan_num()577 uint32_t tdm_ctrl = hw->rx_tdm_ctrl.val; in i2s_ll_rx_set_active_chan_mask()580 hw->rx_tdm_ctrl.val = tdm_ctrl; in i2s_ll_rx_set_active_chan_mask()622 hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = 1; // rx_tdm_tot_chan_num = 2 slots - 1 = 1 in i2s_ll_rx_select_std_slot()
232 } rx_tdm_ctrl; member
234 } rx_tdm_ctrl; member
1003 volatile i2s_rx_tdm_ctrl_reg_t rx_tdm_ctrl; member
1001 volatile i2s_rx_tdm_ctrl_reg_t rx_tdm_ctrl; member
