Searched refs:rx_conf (Results 1 – 10 of 10) sorted by relevance
149 hw->rx_conf.rx_slave_mod = slave_en; in i2s_ll_rx_set_slave_mod()170 hw->rx_conf.rx_reset = 1; in i2s_ll_rx_reset()171 hw->rx_conf.rx_reset = 0; in i2s_ll_rx_reset()192 hw->rx_conf.rx_fifo_reset = 1; in i2s_ll_rx_reset_fifo()193 hw->rx_conf.rx_fifo_reset = 0; in i2s_ll_rx_reset_fifo()386 hw->rx_conf.rx_update = 1; in i2s_ll_rx_start()387 while (hw->rx_conf.rx_update); in i2s_ll_rx_start()388 hw->rx_conf.rx_start = 1; in i2s_ll_rx_start()408 hw->rx_conf.rx_start = 0; in i2s_ll_rx_stop()664 hw->rx_conf.rx_ws_idle_pol = ws_pol_level; in i2s_ll_rx_set_ws_idle_pol()[all …]
158 hw->rx_conf.rx_slave_mod = slave_en; in i2s_ll_rx_set_slave_mod()179 hw->rx_conf.rx_reset = 1; in i2s_ll_rx_reset()180 hw->rx_conf.rx_reset = 0; in i2s_ll_rx_reset()201 hw->rx_conf.rx_fifo_reset = 1; in i2s_ll_rx_reset_fifo()202 hw->rx_conf.rx_fifo_reset = 0; in i2s_ll_rx_reset_fifo()358 hw->rx_conf.rx_bck_div_num = val - 1; in i2s_ll_rx_set_bck_div_num()405 hw->rx_conf.rx_update = 1; in i2s_ll_rx_start()406 while (hw->rx_conf.rx_update); in i2s_ll_rx_start()407 hw->rx_conf.rx_start = 1; in i2s_ll_rx_start()427 hw->rx_conf.rx_start = 0; in i2s_ll_rx_stop()[all …]
157 hw->rx_conf.rx_slave_mod = slave_en; in i2s_ll_rx_set_slave_mod()178 hw->rx_conf.rx_reset = 1; in i2s_ll_rx_reset()179 hw->rx_conf.rx_reset = 0; in i2s_ll_rx_reset()200 hw->rx_conf.rx_fifo_reset = 1; in i2s_ll_rx_reset_fifo()201 hw->rx_conf.rx_fifo_reset = 0; in i2s_ll_rx_reset_fifo()398 hw->rx_conf.rx_update = 1; in i2s_ll_rx_start()399 while (hw->rx_conf.rx_update); in i2s_ll_rx_start()400 hw->rx_conf.rx_start = 1; in i2s_ll_rx_start()420 hw->rx_conf.rx_start = 0; in i2s_ll_rx_stop()676 hw->rx_conf.rx_ws_idle_pol = ws_pol_level; in i2s_ll_rx_set_ws_idle_pol()[all …]
148 hw->rx_conf.rx_slave_mod = slave_en; in i2s_ll_rx_set_slave_mod()169 hw->rx_conf.rx_reset = 1; in i2s_ll_rx_reset()170 hw->rx_conf.rx_reset = 0; in i2s_ll_rx_reset()191 hw->rx_conf.rx_fifo_reset = 1; in i2s_ll_rx_reset_fifo()192 hw->rx_conf.rx_fifo_reset = 0; in i2s_ll_rx_reset_fifo()385 hw->rx_conf.rx_update = 1; in i2s_ll_rx_start()386 while (hw->rx_conf.rx_update); in i2s_ll_rx_start()387 hw->rx_conf.rx_start = 1; in i2s_ll_rx_start()407 hw->rx_conf.rx_start = 0; in i2s_ll_rx_stop()663 hw->rx_conf.rx_ws_idle_pol = ws_pol_level; in i2s_ll_rx_set_ws_idle_pol()[all …]
453 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rx_conf[channel].conf0, div_cnt, div); in rmt_ll_rx_set_channel_clock_div()465 dev->rx_conf[channel].conf1.mem_wr_rst = 1; in rmt_ll_rx_reset_pointer()466 dev->rx_conf[channel].conf1.mem_wr_rst = 0; in rmt_ll_rx_reset_pointer()467 dev->rx_conf[channel].conf1.mem_rst = 1; in rmt_ll_rx_reset_pointer()468 dev->rx_conf[channel].conf1.mem_rst = 0; in rmt_ll_rx_reset_pointer()481 dev->rx_conf[channel].conf1.rx_en = enable; in rmt_ll_rx_enable()483 dev->rx_conf[channel].conf1.conf_update = 1; in rmt_ll_rx_enable()495 dev->rx_conf[channel].conf0.mem_size = block_num; in rmt_ll_rx_set_mem_blocks()508 dev->rx_conf[channel].conf0.idle_thres = thres; in rmt_ll_rx_set_idle_thres()521 dev->rx_conf[channel].conf1.mem_owner = owner; in rmt_ll_rx_set_mem_owner()[all …]
66 } rx_conf[2]; member
83 } rx_conf; member
85 } rx_conf; member
992 volatile i2s_rx_conf_reg_t rx_conf; member
990 volatile i2s_rx_conf_reg_t rx_conf; member
