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Searched refs:reg_val (Results 1 – 25 of 25) sorted by relevance

/hal_espressif-latest/components/esp_psram/esp32s3/
Desp_psram_impl_octal.c225 static void s_print_psram_info(opi_psram_mode_reg_t *reg_val) in s_print_psram_info() argument
227 …ESP_EARLY_LOGI(TAG, "vendor id : 0x%02x (%s)", reg_val->mr1.vendor_id, reg_val->mr1.vendor_id =… in s_print_psram_info()
228 …ESP_EARLY_LOGI(TAG, "dev id : 0x%02x (generation %d)", reg_val->mr2.dev_id, reg_val->mr2.dev… in s_print_psram_info()
229 …ESP_EARLY_LOGI(TAG, "density : 0x%02x (%d Mbit)", reg_val->mr2.density, reg_val->mr2.density … in s_print_psram_info()
230 … reg_val->mr2.density == 0X3 ? 64 : in s_print_psram_info()
231 … reg_val->mr2.density == 0x5 ? 128 : in s_print_psram_info()
232 … reg_val->mr2.density == 0x7 ? 256 : 0); in s_print_psram_info()
233 …ESP_EARLY_LOGI(TAG, "good-die : 0x%02x (%s)", reg_val->mr2.gb, reg_val->mr2.gb == 1 ? "Pass" :… in s_print_psram_info()
234 …ESP_EARLY_LOGI(TAG, "Latency : 0x%02x (%s)", reg_val->mr0.lt, reg_val->mr0.lt == 1 ? "Fixed" … in s_print_psram_info()
235 …ESP_EARLY_LOGI(TAG, "VCC : 0x%02x (%s)", reg_val->mr3.vcc, reg_val->mr3.vcc == 1 ? "3V" :… in s_print_psram_info()
[all …]
/hal_espressif-latest/components/hal/esp32c6/include/hal/
Dgpio_etm_ll.h83 uint32_t reg_val = dev->etm_task_pn_cfg[g_p].val; in gpio_ll_etm_gpio_set_task_channel() local
84 reg_val &= ~(0x07 << (g_idx * 8 + 1)); in gpio_ll_etm_gpio_set_task_channel()
85 reg_val |= ((chan & 0x07) << (g_idx * 8 + 1)); in gpio_ll_etm_gpio_set_task_channel()
86 dev->etm_task_pn_cfg[g_p].val = reg_val; in gpio_ll_etm_gpio_set_task_channel()
100 uint32_t reg_val = dev->etm_task_pn_cfg[g_p].val; in gpio_ll_etm_enable_task_gpio() local
101 reg_val &= ~(0x01 << (g_idx * 8)); in gpio_ll_etm_enable_task_gpio()
102 reg_val |= ((enable & 0x01) << (g_idx * 8)); in gpio_ll_etm_enable_task_gpio()
103 dev->etm_task_pn_cfg[g_p].val = reg_val; in gpio_ll_etm_enable_task_gpio()
Dmmu_ll.h82 uint8_t reg_val = (size == MMU_PAGE_64KB) ? 0 : \ in mmu_ll_set_page_size() local
86 REG_SET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_PAGE_SIZE, reg_val); in mmu_ll_set_page_size()
Dspi_ll.h761 spi_ll_clock_val_t reg_val; in spi_ll_master_set_clock() local
762 int freq = spi_ll_master_cal_clock(fapb, hz, duty_cycle, &reg_val); in spi_ll_master_set_clock()
763 spi_ll_master_set_clock_by_reg(hw, &reg_val); in spi_ll_master_set_clock()
/hal_espressif-latest/components/hal/esp32h2/include/hal/
Dgpio_etm_ll.h83 uint32_t reg_val = dev->etm_task_pn_cfg[g_p].val; in gpio_ll_etm_gpio_set_task_channel() local
84 reg_val &= ~(0x07 << (g_idx * 8 + 1)); in gpio_ll_etm_gpio_set_task_channel()
85 reg_val |= ((chan & 0x07) << (g_idx * 8 + 1)); in gpio_ll_etm_gpio_set_task_channel()
86 dev->etm_task_pn_cfg[g_p].val = reg_val; in gpio_ll_etm_gpio_set_task_channel()
100 uint32_t reg_val = dev->etm_task_pn_cfg[g_p].val; in gpio_ll_etm_enable_task_gpio() local
101 reg_val &= ~(0x01 << (g_idx * 8)); in gpio_ll_etm_enable_task_gpio()
102 reg_val |= ((enable & 0x01) << (g_idx * 8)); in gpio_ll_etm_enable_task_gpio()
103 dev->etm_task_pn_cfg[g_p].val = reg_val; in gpio_ll_etm_enable_task_gpio()
Dmmu_ll.h85 uint8_t reg_val = (size == MMU_PAGE_64KB) ? 0 : \ in mmu_ll_set_page_size() local
89 REG_SET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_PAGE_SIZE, reg_val); in mmu_ll_set_page_size()
Dspi_ll.h763 spi_ll_clock_val_t reg_val; in spi_ll_master_set_clock() local
764 int freq = spi_ll_master_cal_clock(fapb, hz, duty_cycle, &reg_val); in spi_ll_master_set_clock()
765 spi_ll_master_set_clock_by_reg(hw, &reg_val); in spi_ll_master_set_clock()
/hal_espressif-latest/components/hal/esp32/include/hal/
Dadc_ll.h357 uint32_t reg_val = 0; in adc_oneshot_ll_set_output_bits() local
360 reg_val = 0; in adc_oneshot_ll_set_output_bits()
363 reg_val = 1; in adc_oneshot_ll_set_output_bits()
366 reg_val = 2; in adc_oneshot_ll_set_output_bits()
369 reg_val = 3; in adc_oneshot_ll_set_output_bits()
372 reg_val = 3; in adc_oneshot_ll_set_output_bits()
378 SENS.sar_start_force.sar1_bit_width = reg_val; in adc_oneshot_ll_set_output_bits()
379 SENS.sar_read_ctrl.sar1_sample_bit = reg_val; in adc_oneshot_ll_set_output_bits()
381 SENS.sar_start_force.sar2_bit_width = reg_val; in adc_oneshot_ll_set_output_bits()
382 SENS.sar_read_ctrl2.sar2_sample_bit = reg_val; in adc_oneshot_ll_set_output_bits()
Dspi_ll.h644 spi_ll_clock_val_t reg_val; in spi_ll_master_set_clock() local
645 int freq = spi_ll_master_cal_clock(fapb, hz, duty_cycle, &reg_val); in spi_ll_master_set_clock()
646 spi_ll_master_set_clock_by_reg(hw, &reg_val); in spi_ll_master_set_clock()
/hal_espressif-latest/components/esp_hw_support/port/esp32s3/
Dmspi_timing_config.c51 uint32_t reg_val = 0; in mspi_timing_config_set_core_clock() local
55 reg_val = 0; in mspi_timing_config_set_core_clock()
58 reg_val = 1; in mspi_timing_config_set_core_clock()
61 reg_val = 2; in mspi_timing_config_set_core_clock()
64 reg_val = 3; in mspi_timing_config_set_core_clock()
70 mspi_timing_ll_set_core_clock_divider(spi_num, reg_val); in mspi_timing_config_set_core_clock()
/hal_espressif-latest/components/hal/esp32s3/include/hal/
Dmspi_timing_tuning_ll.h191 …uint32_t reg_val = (REG_READ(SPI_MEM_DIN_MODE_REG(spi_num)) & (~(SPI_MEM_DIN0_MODE_M | SPI_MEM_DIN… in mspi_timing_ll_set_flash_din_mode() local
194 REG_WRITE(SPI_MEM_DIN_MODE_REG(spi_num), reg_val); in mspi_timing_ll_set_flash_din_mode()
206 …uint32_t reg_val = (REG_READ(SPI_MEM_DIN_NUM_REG(spi_num)) & (~(SPI_MEM_DIN0_NUM_M | SPI_MEM_DIN1_… in mspi_timing_ll_set_flash_din_num() local
209 REG_WRITE(SPI_MEM_DIN_NUM_REG(spi_num), reg_val); in mspi_timing_ll_set_flash_din_num()
290 …uint32_t reg_val = (REG_READ(SPI_MEM_SPI_SMEM_DIN_MODE_REG(spi_num)) & (~(SPI_MEM_SPI_SMEM_DIN0_MO… in mspi_timing_ll_set_psram_din_mode() local
293 REG_WRITE(SPI_MEM_SPI_SMEM_DIN_MODE_REG(spi_num), reg_val); in mspi_timing_ll_set_psram_din_mode()
305 …uint32_t reg_val = (REG_READ(SPI_MEM_SPI_SMEM_DIN_NUM_REG(spi_num)) & (~(SPI_MEM_SPI_SMEM_DIN0_NUM… in mspi_timing_ll_set_psram_din_num() local
308 REG_WRITE(SPI_MEM_SPI_SMEM_DIN_NUM_REG(spi_num), reg_val); in mspi_timing_ll_set_psram_din_num()
Dmemprot_ll.h58 constrain_reg_fields_t reg_val; in memprot_ll_get_split_addr_from_reg() local
59 reg_val.val = regval; in memprot_ll_get_split_addr_from_reg()
61 uint32_t off = reg_val.splitaddr << I_D_SPLIT_LINE_SHIFT; in memprot_ll_get_split_addr_from_reg()
65 if (reg_val.cat0 == MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) break; in memprot_ll_get_split_addr_from_reg()
67 if (reg_val.cat1 == MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) break; in memprot_ll_get_split_addr_from_reg()
69 if (reg_val.cat2 == MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) break; in memprot_ll_get_split_addr_from_reg()
71 if (reg_val.cat3 == MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) break; in memprot_ll_get_split_addr_from_reg()
73 if (reg_val.cat4 == MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) break; in memprot_ll_get_split_addr_from_reg()
75 if (reg_val.cat5 == MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) break; in memprot_ll_get_split_addr_from_reg()
77 if (reg_val.cat6 == MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) break; in memprot_ll_get_split_addr_from_reg()
Dlcd_ll.h541 uint32_t reg_val = 0; in lcd_ll_set_data_delay_ticks() local
543 reg_val |= (delay & 0x03) << (2 * i); in lcd_ll_set_data_delay_ticks()
545 dev->lcd_data_dout_mode.val = reg_val; in lcd_ll_set_data_delay_ticks()
Dspi_ll.h771 spi_ll_clock_val_t reg_val; in spi_ll_master_set_clock() local
772 int freq = spi_ll_master_cal_clock(fapb, hz, duty_cycle, &reg_val); in spi_ll_master_set_clock()
773 spi_ll_master_set_clock_by_reg(hw, &reg_val); in spi_ll_master_set_clock()
/hal_espressif-latest/components/esp_hw_support/
Dregi2c_ctrl.c72 static DRAM_ATTR uint8_t reg_val[REGI2C_ANA_CALI_BYTE_NUM]; variable
77 reg_val[i] = regi2c_ctrl_read_reg(I2C_SAR_ADC, I2C_SAR_ADC_HOSTID, i); in regi2c_analog_cali_reg_read()
84 regi2c_ctrl_write_reg(I2C_SAR_ADC, I2C_SAR_ADC_HOSTID, i, reg_val[i]); in regi2c_analog_cali_reg_write()
Dsar_periph_ctrl_common.c115 temperature_dac = temperature_sensor_attributes[s_tsens_idx].reg_val; in temp_sensor_get_raw_value()
/hal_espressif-latest/components/driver/deprecated/
Drtc_temperature_legacy.c32 int reg_val; member
66 temperature_sensor_ll_set_range(dac_offset[tsens.dac_offset].reg_val); in temp_sensor_set_config()
80 if ((int)tsens->dac_offset == dac_offset[i].reg_val) { in temp_sensor_get_config()
/hal_espressif-latest/components/hal/esp32c3/include/hal/
Dmemprot_ll.h32 constrain_reg_fields_t reg_val; in memprot_ll_get_split_addr_from_reg() local
33 reg_val.val = regval; in memprot_ll_get_split_addr_from_reg()
35 uint32_t off = reg_val.splitaddr << 9; in memprot_ll_get_split_addr_from_reg()
37 if (reg_val.cat0 == 0x1 || reg_val.cat0 == 0x2) { in memprot_ll_get_split_addr_from_reg()
39 } else if (reg_val.cat1 == 0x1 || reg_val.cat1 == 0x2) { in memprot_ll_get_split_addr_from_reg()
41 } else if (reg_val.cat2 == 0x1 || reg_val.cat2 == 0x2) { in memprot_ll_get_split_addr_from_reg()
Dspi_ll.h757 spi_ll_clock_val_t reg_val; in spi_ll_master_set_clock() local
758 int freq = spi_ll_master_cal_clock(fapb, hz, duty_cycle, &reg_val); in spi_ll_master_set_clock()
759 spi_ll_master_set_clock_by_reg(hw, &reg_val); in spi_ll_master_set_clock()
/hal_espressif-latest/tools/esptool_py/esptool/targets/
Desp32.py379 reg_val = self.RTC_CNTL_SDIO_FORCE # override efuse setting
380 reg_val |= self.RTC_CNTL_SDIO_PD_EN
382 reg_val |= self.RTC_CNTL_XPD_SDIO_REG # enable internal LDO
384 reg_val |= (
389 self.write_reg(self.RTC_CNTL_SDIO_CONF_REG, reg_val)
/hal_espressif-latest/components/spi_flash/esp32s3/
Dspi_flash_oct_flash_init.c135 uint16_t reg_val = 0; in s_set_flash_ouput_driver_strength() local
166 reg_val = (((cr_reg_val & 0xf8) | strength) << 8) | sr_reg_val; in s_set_flash_ouput_driver_strength()
176 (uint8_t*)&reg_val, data_bit_len, in s_set_flash_ouput_driver_strength()
/hal_espressif-latest/components/soc/include/soc/
Dtemperature_sensor_periph.h17 int reg_val; member
/hal_espressif-latest/components/hal/esp32c2/include/hal/
Dmmu_ll.h77 uint8_t reg_val = (size == MMU_PAGE_16KB) ? 0 : (size == MMU_PAGE_32KB) ? 1 : 2; in mmu_ll_set_page_size() local
78 REG_SET_FIELD(EXTMEM_CACHE_CONF_MISC_REG, EXTMEM_CACHE_MMU_PAGE_SIZE, reg_val); in mmu_ll_set_page_size()
Dspi_ll.h757 spi_ll_clock_val_t reg_val; in spi_ll_master_set_clock() local
758 int freq = spi_ll_master_cal_clock(fapb, hz, duty_cycle, &reg_val); in spi_ll_master_set_clock()
759 spi_ll_master_set_clock_by_reg(hw, &reg_val); in spi_ll_master_set_clock()
/hal_espressif-latest/components/hal/esp32s2/include/hal/
Dspi_ll.h719 spi_ll_clock_val_t reg_val; in spi_ll_master_set_clock() local
720 int freq = spi_ll_master_cal_clock(fapb, hz, duty_cycle, &reg_val); in spi_ll_master_set_clock()
721 spi_ll_master_set_clock_by_reg(hw, &reg_val); in spi_ll_master_set_clock()