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Searched refs:faddr_quad (Results 1 – 24 of 24) sorted by relevance

/hal_espressif-latest/components/hal/esp32h2/include/hal/
Dgpspi_flash_ll.h216 ctrl.faddr_quad = 1; in gpspi_flash_ll_set_read_mode()
Dspi_ll.h599 hw->ctrl.faddr_quad = (line_mode.addr_lines == 4); in spi_ll_master_set_line_mode()
/hal_espressif-latest/components/hal/esp32s3/include/hal/
Dgpspi_flash_ll.h221 ctrl.faddr_quad = 1; in gpspi_flash_ll_set_read_mode()
Dspi_ll.h596 hw->ctrl.faddr_quad = (line_mode.addr_lines == 4); in spi_ll_master_set_line_mode()
/hal_espressif-latest/components/hal/esp32s2/include/hal/
Dgpspi_flash_ll.h214 ctrl.faddr_quad = 1; in gpspi_flash_ll_set_read_mode()
Dspi_ll.h558 hw->ctrl.faddr_quad = (line_mode.addr_lines == 4); in spi_ll_master_set_line_mode()
/hal_espressif-latest/components/hal/esp32c6/include/hal/
Dgpspi_flash_ll.h216 ctrl.faddr_quad = 1; in gpspi_flash_ll_set_read_mode()
Dspi_ll.h597 hw->ctrl.faddr_quad = (line_mode.addr_lines == 4); in spi_ll_master_set_line_mode()
/hal_espressif-latest/components/hal/esp32c2/include/hal/
Dgpspi_flash_ll.h216 ctrl.faddr_quad = 1; in gpspi_flash_ll_set_read_mode()
Dspi_ll.h593 hw->ctrl.faddr_quad = (line_mode.addr_lines == 4); in spi_ll_master_set_line_mode()
/hal_espressif-latest/components/hal/esp32c3/include/hal/
Dgpspi_flash_ll.h216 ctrl.faddr_quad = 1; in gpspi_flash_ll_set_read_mode()
Dspi_ll.h593 hw->ctrl.faddr_quad = (line_mode.addr_lines == 4); in spi_ll_master_set_line_mode()
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Dspi_struct.h31 …uint32_t faddr_quad : 1; /*Apply 4 signals during addr phase 1:enable 0: di… member
Dspi_mem_struct.h184 …uint32_t faddr_quad: 1; /*For SPI1 address phase apply 4 signals. 1: enable 0… member
/hal_espressif-latest/components/soc/esp32c2/include/soc/
Dspi_struct.h33 …uint32_t faddr_quad : 1; /*Apply 4 signals during addr phase 1:enable 0: di… member
Dspi_mem_struct.h185 …uint32_t faddr_quad : 1; /*For SPI0 flash, address phase apply 4 signals. 1… member
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Dspi_struct.h41 …uint32_t faddr_quad : 1; /*Apply 4 signals during addr phase 1:enable 0: di… member
Dspi_mem_struct.h195 …uint32_t faddr_quad : 1; /*When SPI0 accesses to flash, set this bit to ena… member
/hal_espressif-latest/components/soc/esp32c6/include/soc/
Dspi_struct.h253 uint32_t faddr_quad:1; member
Dspi_mem_struct.h201 …uint32_t faddr_quad : 1; /*For SPI0 flash, address phase apply 4 signals. 1… member
/hal_espressif-latest/components/soc/esp32h2/include/soc/
Dspi_struct.h253 uint32_t faddr_quad:1; member
Dspi_mem_struct.h202 …uint32_t faddr_quad : 1; /*For SPI0 flash, address phase apply 4 signals. 1… member
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Dspi_mem_struct.h187 …uint32_t faddr_quad: 1; /*For SPI0 flash address phase apply 4 signal… member
Dspi_struct.h32 …uint32_t faddr_quad: 1; /*Apply 4 signals during addr phase 1:enable 0: disa… member