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Searched refs:div (Results 1 – 25 of 70) sorted by relevance

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/hal_espressif-latest/components/esp_hw_support/port/esp32c2/
Drtc_clk.c31 void rtc_clk_cpu_freq_to_xtal(int freq, int div);
187 .div = divider, in rtc_clk_cpu_freq_mhz_to_config()
198 rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div); in rtc_clk_cpu_freq_set_config()
220 uint32_t div; in rtc_clk_cpu_freq_get_config() local
224 div = clk_ll_cpu_get_divider(); in rtc_clk_cpu_freq_get_config()
226 freq_mhz = source_freq_mhz / div; in rtc_clk_cpu_freq_get_config()
233 div = 6; in rtc_clk_cpu_freq_get_config()
235 div = 4; in rtc_clk_cpu_freq_get_config()
244 div = 1; in rtc_clk_cpu_freq_get_config()
254 .div = div, in rtc_clk_cpu_freq_get_config()
[all …]
/hal_espressif-latest/components/esp_hw_support/port/esp32c3/
Drtc_clk.c27 static void rtc_clk_cpu_freq_to_xtal(int freq, int div);
212 .div = divider, in rtc_clk_cpu_freq_mhz_to_config()
223 rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div); in rtc_clk_cpu_freq_set_config()
247 uint32_t div; in rtc_clk_cpu_freq_get_config() local
251 div = clk_ll_cpu_get_divider(); in rtc_clk_cpu_freq_get_config()
253 freq_mhz = source_freq_mhz / div; in rtc_clk_cpu_freq_get_config()
260 div = (source_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ) ? 6 : 4; in rtc_clk_cpu_freq_get_config()
262 div = (source_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ) ? 3 : 2; in rtc_clk_cpu_freq_get_config()
271 div = 1; in rtc_clk_cpu_freq_get_config()
281 .div = div, in rtc_clk_cpu_freq_get_config()
[all …]
/hal_espressif-latest/components/esp_hw_support/port/esp32s2/
Drtc_clk.c30 static void rtc_clk_cpu_freq_to_xtal(int freq, int div);
335 .div = divider, in rtc_clk_cpu_freq_mhz_to_config()
353 if (config->div > 1) { in rtc_clk_cpu_freq_set_config()
354 rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div); in rtc_clk_cpu_freq_set_config()
369 uint32_t div; in rtc_clk_cpu_freq_get_config() local
373 div = clk_ll_cpu_get_divider(); in rtc_clk_cpu_freq_get_config()
375 freq_mhz = source_freq_mhz / div; in rtc_clk_cpu_freq_get_config()
382 div = (source_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ) ? 6 : 4; in rtc_clk_cpu_freq_get_config()
384 div = (source_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ) ? 3 : 2; in rtc_clk_cpu_freq_get_config()
386 div = 2; in rtc_clk_cpu_freq_get_config()
[all …]
/hal_espressif-latest/components/esp_hw_support/port/esp32s3/
Drtc_clk.c34 void rtc_clk_cpu_freq_to_xtal(int freq, int div);
271 .div = divider, in rtc_clk_cpu_freq_mhz_to_config()
282 rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div); in rtc_clk_cpu_freq_set_config()
306 uint32_t div; in rtc_clk_cpu_freq_get_config() local
310 div = clk_ll_cpu_get_divider(); in rtc_clk_cpu_freq_get_config()
312 freq_mhz = source_freq_mhz / div; in rtc_clk_cpu_freq_get_config()
319 div = (source_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ) ? 6 : 4; in rtc_clk_cpu_freq_get_config()
321 div = (source_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ) ? 3 : 2; in rtc_clk_cpu_freq_get_config()
323 div = 2; in rtc_clk_cpu_freq_get_config()
332 div = 1; in rtc_clk_cpu_freq_get_config()
[all …]
/hal_espressif-latest/components/esp_hw_support/port/esp32c6/
Drtc_clk.c188 static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div) in rtc_clk_cpu_freq_to_xtal() argument
190 clk_ll_ahb_set_ls_divider(div); in rtc_clk_cpu_freq_to_xtal()
191 clk_ll_cpu_set_ls_divider(div); in rtc_clk_cpu_freq_to_xtal()
255 .div = divider, in rtc_clk_cpu_freq_mhz_to_config()
270 rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div); in rtc_clk_cpu_freq_set_config()
296 uint32_t div; // div = freq of SOC_ROOT_CLK / freq of CPU_CLK in rtc_clk_cpu_freq_get_config() local
300 div = clk_ll_cpu_get_ls_divider(); in rtc_clk_cpu_freq_get_config()
302 freq_mhz = source_freq_mhz / div; in rtc_clk_cpu_freq_get_config()
306 div = clk_ll_cpu_get_hs_divider(); in rtc_clk_cpu_freq_get_config()
308 freq_mhz = source_freq_mhz / div; in rtc_clk_cpu_freq_get_config()
[all …]
/hal_espressif-latest/components/esp_hw_support/port/esp32h2/
Drtc_clk.c200 static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div) in rtc_clk_cpu_freq_to_xtal() argument
203 clk_ll_cpu_set_divider(div); in rtc_clk_cpu_freq_to_xtal()
204 clk_ll_ahb_set_divider(div); in rtc_clk_cpu_freq_to_xtal()
295 .div = divider, in rtc_clk_cpu_freq_mhz_to_config()
310 rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div); in rtc_clk_cpu_freq_set_config()
337 rtc_clk_cpu_freq_to_flash_pll(config->freq_mhz, config->div); in rtc_clk_cpu_freq_set_config()
346 uint32_t div = clk_ll_cpu_get_divider(); // div = freq of SOC_ROOT_CLK / freq of CPU_CLK in rtc_clk_cpu_freq_get_config() local
351 freq_mhz = source_freq_mhz / div; in rtc_clk_cpu_freq_get_config()
356 freq_mhz = source_freq_mhz / div; in rtc_clk_cpu_freq_get_config()
361 freq_mhz = source_freq_mhz / div; in rtc_clk_cpu_freq_get_config()
[all …]
/hal_espressif-latest/components/esp_hw_support/port/esp32/
Drtc_clk.c354 void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div) in rtc_clk_cpu_freq_to_xtal() argument
358 clk_ll_cpu_set_divider(div); in rtc_clk_cpu_freq_to_xtal()
453 .div = divider, in rtc_clk_cpu_freq_mhz_to_config()
473 if (config->div > 1) { in rtc_clk_cpu_freq_set_config()
474 rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div); in rtc_clk_cpu_freq_set_config()
490 uint32_t div; in rtc_clk_cpu_freq_get_config() local
494 div = clk_ll_cpu_get_divider(); in rtc_clk_cpu_freq_get_config()
496 freq_mhz = source_freq_mhz / div; in rtc_clk_cpu_freq_get_config()
503 div = 4; in rtc_clk_cpu_freq_get_config()
506 div = 2; in rtc_clk_cpu_freq_get_config()
[all …]
/hal_espressif-latest/components/hal/esp32/include/hal/
Drmt_ll.h162 static inline void rmt_ll_tx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) in rmt_ll_tx_set_channel_clock_div() argument
164 HAL_ASSERT(div >= 1 && div <= 256 && "divider out of range"); in rmt_ll_tx_set_channel_clock_div()
166 if (div >= 256) { in rmt_ll_tx_set_channel_clock_div()
167 div = 0; // 0 means 256 division in rmt_ll_tx_set_channel_clock_div()
169 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt, div); in rmt_ll_tx_set_channel_clock_div()
333 static inline void rmt_ll_rx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) in rmt_ll_rx_set_channel_clock_div() argument
335 HAL_ASSERT(div >= 1 && div <= 256 && "divider out of range"); in rmt_ll_rx_set_channel_clock_div()
337 if (div >= 256) { in rmt_ll_rx_set_channel_clock_div()
338 div = 0; // 0 means 256 division in rmt_ll_rx_set_channel_clock_div()
340 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt, div); in rmt_ll_rx_set_channel_clock_div()
[all …]
Dsdmmc_ll.h96 static inline void sdmmc_ll_set_clock_div(sdmmc_dev_t *hw, uint32_t div) in sdmmc_ll_set_clock_div() argument
107 HAL_ASSERT(div > 1 && div <= 16); in sdmmc_ll_set_clock_div()
108 int h = div - 1; in sdmmc_ll_set_clock_div()
109 int l = div / 2 - 1; in sdmmc_ll_set_clock_div()
Dadc_ll.h131 static inline void adc_ll_digi_set_clk_div(uint32_t div) in adc_ll_digi_set_clk_div() argument
134 HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_ctrl, sar_clk_div, div); in adc_ll_digi_set_clk_div()
340 static inline void adc_ll_set_sar_clk_div(adc_unit_t adc_n, uint32_t div) in adc_ll_set_sar_clk_div() argument
343 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_read_ctrl, sar1_clk_div, div); in adc_ll_set_sar_clk_div()
345 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_read_ctrl2, sar2_clk_div, div); in adc_ll_set_sar_clk_div()
/hal_espressif-latest/components/hal/esp32s2/include/hal/
Drmt_ll.h165 static inline void rmt_ll_tx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) in rmt_ll_tx_set_channel_clock_div() argument
167 HAL_ASSERT(div >= 1 && div <= 256 && "divider out of range"); in rmt_ll_tx_set_channel_clock_div()
169 if (div >= 256) { in rmt_ll_tx_set_channel_clock_div()
170 div = 0; // 0 means 256 division in rmt_ll_tx_set_channel_clock_div()
172 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt_chn, div); in rmt_ll_tx_set_channel_clock_div()
440 static inline void rmt_ll_rx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) in rmt_ll_rx_set_channel_clock_div() argument
442 HAL_ASSERT(div >= 1 && div <= 256 && "divider out of range"); in rmt_ll_rx_set_channel_clock_div()
444 if (div >= 256) { in rmt_ll_rx_set_channel_clock_div()
445 div = 0; // 0 means 256 division in rmt_ll_rx_set_channel_clock_div()
447 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt_chn, div); in rmt_ll_rx_set_channel_clock_div()
[all …]
Dadc_ll.h169 static inline void adc_ll_digi_set_clk_div(uint32_t div) in adc_ll_digi_set_clk_div() argument
172 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl, sar_clk_div, div); in adc_ll_digi_set_clk_div()
579 static inline void adc_ll_set_sar_clk_div(adc_unit_t adc_n, uint32_t div) in adc_ll_set_sar_clk_div() argument
582 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_reader1_ctrl, sar1_clk_div, div); in adc_ll_set_sar_clk_div()
584 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_reader2_ctrl, sar2_clk_div, div); in adc_ll_set_sar_clk_div()
/hal_espressif-latest/components/hal/esp32s3/include/hal/
Drmt_ll.h167 static inline void rmt_ll_tx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) in rmt_ll_tx_set_channel_clock_div() argument
169 HAL_ASSERT(div >= 1 && div <= 256 && "divider out of range"); in rmt_ll_tx_set_channel_clock_div()
171 if (div >= 256) { in rmt_ll_tx_set_channel_clock_div()
172 div = 0; // 0 means 256 division in rmt_ll_tx_set_channel_clock_div()
174 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chnconf0[channel], div_cnt_chn, div); in rmt_ll_tx_set_channel_clock_div()
471 static inline void rmt_ll_rx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) in rmt_ll_rx_set_channel_clock_div() argument
473 HAL_ASSERT(div >= 1 && div <= 256 && "divider out of range"); in rmt_ll_rx_set_channel_clock_div()
475 if (div >= 256) { in rmt_ll_rx_set_channel_clock_div()
476 div = 0; // 0 means 256 division in rmt_ll_rx_set_channel_clock_div()
478 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chmconf[channel].conf0, div_cnt_chm, div); in rmt_ll_rx_set_channel_clock_div()
[all …]
Dsdmmc_ll.h72 static inline void sdmmc_ll_set_clock_div(sdmmc_dev_t *hw, uint32_t div) in sdmmc_ll_set_clock_div() argument
84 HAL_ASSERT(div > 1 && div <= 16); in sdmmc_ll_set_clock_div()
85 int l = div - 1; in sdmmc_ll_set_clock_div()
86 int h = div / 2 - 1; in sdmmc_ll_set_clock_div()
Dadc_ll.h179 static inline void adc_ll_digi_set_clk_div(uint32_t div) in adc_ll_digi_set_clk_div() argument
182 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl, sar_clk_div, div); in adc_ll_digi_set_clk_div()
830 static inline void adc_ll_set_sar_clk_div(adc_unit_t adc_n, uint32_t div) in adc_ll_set_sar_clk_div() argument
833 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_reader1_ctrl, sar1_clk_div, div); in adc_ll_set_sar_clk_div()
835 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_reader2_ctrl, sar2_clk_div, div); in adc_ll_set_sar_clk_div()
/hal_espressif-latest/components/hal/esp32c6/include/hal/
Drmt_ll.h169 static inline void rmt_ll_tx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) in rmt_ll_tx_set_channel_clock_div() argument
171 HAL_ASSERT(div >= 1 && div <= 256 && "divider out of range"); in rmt_ll_tx_set_channel_clock_div()
173 if (div >= 256) { in rmt_ll_tx_set_channel_clock_div()
174 div = 0; // 0 means 256 division in rmt_ll_tx_set_channel_clock_div()
176 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chnconf0[channel], div_cnt_chn, div); in rmt_ll_tx_set_channel_clock_div()
461 static inline void rmt_ll_rx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) in rmt_ll_rx_set_channel_clock_div() argument
463 HAL_ASSERT(div >= 1 && div <= 256 && "divider out of range"); in rmt_ll_rx_set_channel_clock_div()
465 if (div >= 256) { in rmt_ll_rx_set_channel_clock_div()
466 div = 0; // 0 means 256 division in rmt_ll_rx_set_channel_clock_div()
468 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chmconf[channel].conf0, div_cnt_chm, div); in rmt_ll_rx_set_channel_clock_div()
[all …]
Dparlio_ll.h86 static inline void parlio_ll_rx_set_clock_div(parl_io_dev_t *dev, uint32_t div) in parlio_ll_rx_set_clock_div() argument
89 HAL_ASSERT(div > 0 && div <= PARLIO_LL_RX_MAX_CLOCK_DIV); in parlio_ll_rx_set_clock_div()
90 HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.parl_clk_rx_conf, parl_clk_rx_div_num, div - 1); in parlio_ll_rx_set_clock_div()
368 static inline void parlio_ll_tx_set_clock_div(parl_io_dev_t *dev, uint32_t div) in parlio_ll_tx_set_clock_div() argument
371 HAL_ASSERT(div > 0 && div <= PARLIO_LL_TX_MAX_CLOCK_DIV); in parlio_ll_tx_set_clock_div()
372 HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.parl_clk_tx_conf, parl_clk_tx_div_num, div - 1); in parlio_ll_tx_set_clock_div()
/hal_espressif-latest/components/hal/esp32c3/include/hal/
Drmt_ll.h167 static inline void rmt_ll_tx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) in rmt_ll_tx_set_channel_clock_div() argument
169 HAL_ASSERT(div >= 1 && div <= 256 && "divider out of range"); in rmt_ll_tx_set_channel_clock_div()
171 if (div >= 256) { in rmt_ll_tx_set_channel_clock_div()
172 div = 0; // 0 means 256 division in rmt_ll_tx_set_channel_clock_div()
174 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->tx_conf[channel], div_cnt, div); in rmt_ll_tx_set_channel_clock_div()
446 static inline void rmt_ll_rx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) in rmt_ll_rx_set_channel_clock_div() argument
448 HAL_ASSERT(div >= 1 && div <= 256 && "divider out of range"); in rmt_ll_rx_set_channel_clock_div()
450 if (div >= 256) { in rmt_ll_rx_set_channel_clock_div()
451 div = 0; // 0 means 256 division in rmt_ll_rx_set_channel_clock_div()
453 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rx_conf[channel].conf0, div_cnt, div); in rmt_ll_rx_set_channel_clock_div()
[all …]
/hal_espressif-latest/components/hal/esp32h2/include/hal/
Drmt_ll.h166 static inline void rmt_ll_tx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) in rmt_ll_tx_set_channel_clock_div() argument
168 HAL_ASSERT(div >= 1 && div <= 256 && "divider out of range"); in rmt_ll_tx_set_channel_clock_div()
170 if (div >= 256) { in rmt_ll_tx_set_channel_clock_div()
171 div = 0; // 0 means 256 division in rmt_ll_tx_set_channel_clock_div()
173 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chnconf0[channel], div_cnt_chn, div); in rmt_ll_tx_set_channel_clock_div()
458 static inline void rmt_ll_rx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) in rmt_ll_rx_set_channel_clock_div() argument
460 HAL_ASSERT(div >= 1 && div <= 256 && "divider out of range"); in rmt_ll_rx_set_channel_clock_div()
462 if (div >= 256) { in rmt_ll_rx_set_channel_clock_div()
463 div = 0; // 0 means 256 division in rmt_ll_rx_set_channel_clock_div()
465 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chmconf[channel].conf0, div_cnt_chm, div); in rmt_ll_rx_set_channel_clock_div()
[all …]
Dparlio_ll.h86 static inline void parlio_ll_rx_set_clock_div(parl_io_dev_t *dev, uint32_t div) in parlio_ll_rx_set_clock_div() argument
89 HAL_ASSERT(div > 0 && div <= PARLIO_LL_RX_MAX_CLOCK_DIV); in parlio_ll_rx_set_clock_div()
90 HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.parl_clk_rx_conf, parl_clk_rx_div_num, div - 1); in parlio_ll_rx_set_clock_div()
372 static inline void parlio_ll_tx_set_clock_div(parl_io_dev_t *dev, uint32_t div) in parlio_ll_tx_set_clock_div() argument
375 HAL_ASSERT(div > 0 && div <= PARLIO_LL_TX_MAX_CLOCK_DIV); in parlio_ll_tx_set_clock_div()
376 HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.parl_clk_tx_conf, parl_clk_tx_div_num, div - 1); in parlio_ll_tx_set_clock_div()
/hal_espressif-latest/components/bt/host/bluedroid/bta/av/
Dbta_av_sbc.c68 bta_av_sbc_ups_cb.div = 1; in bta_av_sbc_init_up_sample()
71 bta_av_sbc_ups_cb.div = 2; in bta_av_sbc_init_up_sample()
77 bta_av_sbc_ups_cb.div = 2; in bta_av_sbc_init_up_sample()
80 bta_av_sbc_ups_cb.div = 4; in bta_av_sbc_init_up_sample()
118 src = src_samples / bta_av_sbc_ups_cb.div; in bta_av_sbc_up_sample()
119 dst = dst_samples / bta_av_sbc_ups_cb.div; in bta_av_sbc_up_sample()
/hal_espressif-latest/components/soc/esp32c2/include/soc/
Drtc.h154 uint32_t div; //!< Divider, freq_mhz = source_freq_mhz / div member
229 void rtc_clk_divider_set(uint32_t div);
231 void rtc_clk_8m_divider_set(uint32_t div);
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Drtc.h155 uint32_t div; //!< Divider, freq_mhz = source_freq_mhz / div member
228 void rtc_clk_divider_set(uint32_t div);
230 void rtc_clk_8m_divider_set(uint32_t div);
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Drtc.h161 uint32_t div; //!< Divider, freq_mhz = source_freq_mhz / div member
242 void rtc_clk_divider_set(uint32_t div);
244 void rtc_clk_8m_divider_set(uint32_t div);
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Drtc.h159 uint32_t div; //!< Divider, freq_mhz = source_freq_mhz / div member
232 void rtc_clk_divider_set(uint32_t div);
234 void rtc_clk_8m_divider_set(uint32_t div);

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