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Searched refs:TIMG_T0_DIVCNT_RST_V (Results 1 – 4 of 4) sorted by relevance

/hal_espressif-latest/components/soc/esp32c6/include/soc/
Dtimer_group_reg.h62 #define TIMG_T0_DIVCNT_RST_M (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S)
63 #define TIMG_T0_DIVCNT_RST_V 0x00000001U macro
/hal_espressif-latest/components/soc/esp32c2/include/soc/
Dtimer_group_reg.h59 #define TIMG_T0_DIVCNT_RST_M (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S)
60 #define TIMG_T0_DIVCNT_RST_V 0x00000001U macro
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Dtimer_group_reg.h59 #define TIMG_T0_DIVCNT_RST_M (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S)
60 #define TIMG_T0_DIVCNT_RST_V 0x00000001U macro
/hal_espressif-latest/components/soc/esp32h2/include/soc/
Dtimer_group_reg.h62 #define TIMG_T0_DIVCNT_RST_M (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S)
63 #define TIMG_T0_DIVCNT_RST_V 0x00000001U macro