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Searched refs:RTC_CNTL_SDIO_CONF_REG (Results 1 – 12 of 12) sorted by relevance

/hal_espressif-latest/components/esp_hw_support/port/esp32/
Drtc_init.c121 uint32_t sdio_conf_reg = REG_READ(RTC_CNTL_SDIO_CONF_REG); in rtc_vddsdio_get_config()
167 REG_WRITE(RTC_CNTL_SDIO_CONF_REG, val); in rtc_vddsdio_set_config()
Drtc_sleep.c225 REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE); in rtc_sleep_init()
226 REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_PD_EN, cfg.vddsdio_pd_en); in rtc_sleep_init()
/hal_espressif-latest/tools/esptool_py/esptool/targets/
Desp32.py76 RTC_CNTL_SDIO_CONF_REG = 0x3FF48074 variable in ESP32ROM
345 reg = self.read_reg(self.RTC_CNTL_SDIO_CONF_REG)
389 self.write_reg(self.RTC_CNTL_SDIO_CONF_REG, reg_val)
/hal_espressif-latest/components/esp_hw_support/port/esp32s2/
Drtc_init.c188 uint32_t sdio_conf_reg = REG_READ(RTC_CNTL_SDIO_CONF_REG); in rtc_vddsdio_get_config()
228 REG_WRITE(RTC_CNTL_SDIO_CONF_REG, val); in rtc_vddsdio_set_config()
Drtc_sleep.c242 REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE); in rtc_sleep_init()
243 REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_PD_EN, cfg.vddsdio_pd_en); in rtc_sleep_init()
/hal_espressif-latest/components/esp_hw_support/port/esp32c3/
Drtc_sleep.c237 REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE); in rtc_sleep_init()
238 REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_PD_EN, cfg.vddsdio_pd_en); in rtc_sleep_init()
/hal_espressif-latest/components/esp_hw_support/port/esp32s3/
Drtc_sleep.c247 REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE); in rtc_sleep_init()
248 REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_PD_EN, cfg.vddsdio_pd_en); in rtc_sleep_init()
Drtc_init.c217 uint32_t sdio_conf_reg = REG_READ(RTC_CNTL_SDIO_CONF_REG); in rtc_vddsdio_get_config()
247 REG_WRITE(RTC_CNTL_SDIO_CONF_REG, val); in rtc_vddsdio_set_config()
/hal_espressif-latest/components/soc/esp32/include/soc/
Drtc_cntl_reg.h975 #define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x74) macro
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Drtc_cntl_reg.h1122 #define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0078) macro
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Drtc_cntl_reg.h1327 #define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x007C) macro
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Drtc_cntl_reg.h1431 #define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x7C) macro