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Searched refs:RTC_CNTL_GLITCH_RST_EN (Results 1 – 7 of 7) sorted by relevance

/hal_espressif-latest/components/bootloader_support/src/esp32c3/
Dbootloader_soc.c37 REG_SET_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN); in bootloader_ana_clock_glitch_reset_config()
39 REG_CLR_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN); in bootloader_ana_clock_glitch_reset_config()
/hal_espressif-latest/components/bootloader_support/src/esp32s3/
Dbootloader_soc.c37 REG_SET_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN); in bootloader_ana_clock_glitch_reset_config()
39 REG_CLR_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN); in bootloader_ana_clock_glitch_reset_config()
/hal_espressif-latest/zephyr/esp32c3/src/
Dsoc_init.c56 REG_SET_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN); in ana_clock_glitch_reset_config()
58 REG_CLR_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN); in ana_clock_glitch_reset_config()
/hal_espressif-latest/zephyr/esp32s3/src/
Dsoc_init.c45 REG_SET_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN); in ana_clock_glitch_reset_config()
47 REG_CLR_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN); in ana_clock_glitch_reset_config()
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Drtc_cntl_reg.h455 #define RTC_CNTL_GLITCH_RST_EN (BIT(20)) macro
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Drtc_cntl_reg.h469 #define RTC_CNTL_GLITCH_RST_EN (BIT(20)) macro
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Drtc_cntl_reg.h456 #define RTC_CNTL_GLITCH_RST_EN (BIT(20)) macro