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Searched refs:RTC_CNTL_FIB_GLITCH_RST (Results 1 – 7 of 7) sorted by relevance

/hal_espressif-latest/components/bootloader_support/src/esp32c3/
Dbootloader_soc.c34 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_GLITCH_RST); in bootloader_ana_clock_glitch_reset_config()
/hal_espressif-latest/components/bootloader_support/src/esp32s3/
Dbootloader_soc.c34 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_GLITCH_RST); in bootloader_ana_clock_glitch_reset_config()
/hal_espressif-latest/zephyr/esp32c3/src/
Dsoc_init.c53 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_GLITCH_RST); in ana_clock_glitch_reset_config()
/hal_espressif-latest/zephyr/esp32s3/src/
Dsoc_init.c42 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_GLITCH_RST); in ana_clock_glitch_reset_config()
/hal_espressif-latest/components/soc/esp32c2/include/soc/
Drtc_cntl_reg.h1681 #define RTC_CNTL_FIB_GLITCH_RST BIT(0) macro
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Drtc_cntl_reg.h2355 #define RTC_CNTL_FIB_GLITCH_RST BIT(0) macro
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Drtc_cntl_reg.h3573 #define RTC_CNTL_FIB_GLITCH_RST BIT(0) macro