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Searched refs:RSA_MEM_RB_BLOCK_BASE (Results 1 – 8 of 8) sorted by relevance

/hal_espressif-latest/components/mbedtls/port/esp32s2/
Dbignum.c146 mpi_to_mem_block(RSA_MEM_RB_BLOCK_BASE, Rinv, num_words); in esp_mpi_mul_mpi_mod_hw_op()
164 mpi_to_mem_block(RSA_MEM_RB_BLOCK_BASE, Rinv, num_words); in esp_mpi_exp_mpi_mod_hw_op()
216 DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE, 1); in esp_mpi_mult_mpi_failover_mod_mult_hw_op()
220 DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE + i * 4, 0); in esp_mpi_mult_mpi_failover_mod_mult_hw_op()
/hal_espressif-latest/components/mbedtls/port/esp32s3/
Dbignum.c148 mpi_to_mem_block(RSA_MEM_RB_BLOCK_BASE, Rinv, num_words); in esp_mpi_mul_mpi_mod_hw_op()
166 mpi_to_mem_block(RSA_MEM_RB_BLOCK_BASE, Rinv, num_words); in esp_mpi_exp_mpi_mod_hw_op()
218 DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE, 1); in esp_mpi_mult_mpi_failover_mod_mult_hw_op()
222 DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE + i * 4, 0); in esp_mpi_mult_mpi_failover_mod_mult_hw_op()
/hal_espressif-latest/components/mbedtls/port/esp32c3/
Dbignum.c151 mpi_to_mem_block(RSA_MEM_RB_BLOCK_BASE, Rinv, num_words); in esp_mpi_mul_mpi_mod_hw_op()
169 mpi_to_mem_block(RSA_MEM_RB_BLOCK_BASE, Rinv, num_words); in esp_mpi_exp_mpi_mod_hw_op()
221 REG_WRITE(RSA_MEM_RB_BLOCK_BASE, 1); in esp_mpi_mult_mpi_failover_mod_mult_hw_op()
225 REG_WRITE(RSA_MEM_RB_BLOCK_BASE + i * 4, 0); in esp_mpi_mult_mpi_failover_mod_mult_hw_op()
/hal_espressif-latest/components/mbedtls/port/esp32/
Dbignum.c166 mpi_to_mem_block(RSA_MEM_RB_BLOCK_BASE, Rinv, hw_words); in esp_mpi_mul_mpi_mod_hw_op()
222 mpi_to_mem_block(RSA_MEM_RB_BLOCK_BASE, Y, hw_words); in esp_mont_hw_op()
279 DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE, 1); in esp_mpi_mult_mpi_failover_mod_mult_hw_op()
283 DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE + i * 4, 0); in esp_mpi_mult_mpi_failover_mod_mult_hw_op()
/hal_espressif-latest/components/soc/esp32/include/soc/
Dhwcrypto_reg.h22 #define RSA_MEM_RB_BLOCK_BASE ((DR_REG_RSA_BASE)+0x200) macro
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Dhwcrypto_reg.h14 #define RSA_MEM_RB_BLOCK_BASE ((DR_REG_RSA_BASE)+0x200) macro
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Dhwcrypto_reg.h15 #define RSA_MEM_RB_BLOCK_BASE ((DR_REG_RSA_BASE)+0x200) macro
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Dhwcrypto_reg.h15 #define RSA_MEM_RB_BLOCK_BASE ((DR_REG_RSA_BASE)+0x200) macro