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Searched refs:RSA_INTERRUPT_REG (Results 1 – 8 of 8) sorted by relevance

/hal_espressif-latest/components/mbedtls/port/esp32/
Dbignum.c56 DPORT_REG_WRITE(RSA_INTERRUPT_REG, enable); in esp_mpi_interrupt_enable()
134 DPORT_REG_WRITE(RSA_INTERRUPT_REG, 1); in start_op()
146 while (DPORT_REG_READ(RSA_INTERRUPT_REG) != 1) in wait_op_complete()
150 DPORT_REG_WRITE(RSA_INTERRUPT_REG, 1); in wait_op_complete()
/hal_espressif-latest/components/mbedtls/port/esp32s2/
Dbignum.c38 REG_WRITE(RSA_INTERRUPT_REG, 0); in esp_mpi_enable_hardware_hw_op()
53 REG_WRITE(RSA_INTERRUPT_REG, enable); in esp_mpi_interrupt_enable()
/hal_espressif-latest/components/mbedtls/port/esp32s3/
Dbignum.c39 REG_WRITE(RSA_INTERRUPT_REG, 0); in esp_mpi_enable_hardware_hw_op()
55 REG_WRITE(RSA_INTERRUPT_REG, enable); in esp_mpi_interrupt_enable()
/hal_espressif-latest/components/mbedtls/port/esp32c3/
Dbignum.c40 REG_WRITE(RSA_INTERRUPT_REG, 0); in esp_mpi_enable_hardware_hw_op()
55 REG_WRITE(RSA_INTERRUPT_REG, enable); in esp_mpi_interrupt_enable()
/hal_espressif-latest/components/soc/esp32/include/soc/
Dhwcrypto_reg.h40 #define RSA_INTERRUPT_REG (RSA_CLEAR_INTERRUPT_REG) macro
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Dhwcrypto_reg.h37 #define RSA_INTERRUPT_REG (DR_REG_RSA_BASE + 0x82C) macro
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Dhwcrypto_reg.h38 #define RSA_INTERRUPT_REG (DR_REG_RSA_BASE + 0x82C) macro
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Dhwcrypto_reg.h38 #define RSA_INTERRUPT_REG (DR_REG_RSA_BASE + 0x82C) macro