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Searched refs:REG_WRITE (Results 1 – 25 of 120) sorted by relevance

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/hal_espressif-latest/components/hal/esp32s3/include/hal/
Dhmac_ll.h35 REG_WRITE(HMAC_SET_START_REG, 1); in hmac_ll_start()
48 REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, HMAC_LL_EFUSE_KEY_PURPOSE_UP); in hmac_ll_config_output()
51 REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, HMAC_LL_EFUSE_KEY_PURPOSE_DOWN_DIGITAL_SIGNATURE); in hmac_ll_config_output()
54 REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, HMAC_LL_EFUSE_KEY_PURPOSE_DOWN_JTAG); in hmac_ll_config_output()
57 REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, HMAC_LL_EFUSE_KEY_PURPOSE_DOWN_ALL); in hmac_ll_config_output()
69 REG_WRITE(HMAC_SET_PARA_KEY_REG, key_id); in hmac_ll_config_hw_key_id()
79 REG_WRITE(HMAC_SET_PARA_FINISH_REG, 1); in hmac_ll_config_finish()
113 REG_WRITE(HMAC_WDATA_BASE + (i * REG_WIDTH), block[i]); in hmac_ll_write_block_512()
116 REG_WRITE(HMAC_SET_MESSAGE_ONE_REG, 1); in hmac_ll_write_block_512()
135 REG_WRITE(HMAC_SET_INVALIDATE_DS_REG, 1); in hmac_ll_clean()
[all …]
Dsha_ll.h33 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_start_block()
34 REG_WRITE(SHA_START_REG, 1); in sha_ll_start_block()
44 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_continue_block()
45 REG_WRITE(SHA_CONTINUE_REG, 1); in sha_ll_continue_block()
55 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_start_dma()
56 REG_WRITE(SHA_DMA_START_REG, 1); in sha_ll_start_dma()
66 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_continue_dma()
67 REG_WRITE(SHA_DMA_CONTINUE_REG, 1); in sha_ll_continue_dma()
90 REG_WRITE(SHA_BLOCK_NUM_REG, num_blocks); in sha_ll_set_block_num()
116 REG_WRITE(&reg_addr_buf[i], data_words[i]); in sha_ll_fill_text_block()
[all …]
Daes_ll.h45 REG_WRITE(AES_KEY_BASE + i * 4, key_word); in aes_ll_write_key()
63 REG_WRITE(AES_MODE_REG, mode_reg_base + ((key_bytes / 8) - 2)); in aes_ll_set_mode()
77 REG_WRITE(AES_TEXT_IN_BASE + i * 4, input_word); in aes_ll_write_block()
104 REG_WRITE(AES_TRIGGER_REG, 1); in aes_ll_start_transform()
128 REG_WRITE(AES_BLOCK_MODE_REG, mode); in aes_ll_set_block_mode()
139 REG_WRITE(AES_INC_SEL_REG, 0); in aes_ll_set_inc()
148 REG_WRITE(AES_DMA_EXIT_REG, 0); in aes_ll_dma_exit()
160 REG_WRITE(AES_BLOCK_NUM_REG, num_blocks); in aes_ll_set_num_blocks()
174 REG_WRITE(&reg_addr_buf[i], iv_word); in aes_ll_set_iv()
200 REG_WRITE(AES_DMA_ENABLE_REG, enable); in aes_ll_dma_enable()
[all …]
Dspi_flash_encrypted_ll.h71 REG_WRITE(AES_XTS_DESTINATION_REG, type); in spi_flash_encrypt_ll_type()
82 REG_WRITE(AES_XTS_SIZE_REG, size >> 5); in spi_flash_encrypt_ll_buffer_length()
106 REG_WRITE(AES_XTS_PHYSICAL_ADDR_REG, flash_addr); in spi_flash_encrypt_ll_address_save()
114 REG_WRITE(AES_XTS_TRIGGER_REG, 1); in spi_flash_encrypt_ll_calculate_start()
131 REG_WRITE(AES_XTS_RELEASE_REG, 1); in spi_flash_encrypt_ll_done()
141 REG_WRITE(AES_XTS_DESTROY_REG, 1); in spi_flash_encrypt_ll_destroy()
/hal_espressif-latest/components/hal/esp32c6/include/hal/
Dhmac_ll.h38 REG_WRITE(HMAC_SET_START_REG, 1); in hmac_ll_start()
51 REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_UP); in hmac_ll_config_output()
54 REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE); in hmac_ll_config_output()
57 REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG); in hmac_ll_config_output()
60 REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL); in hmac_ll_config_output()
72 REG_WRITE(HMAC_SET_PARA_KEY_REG, key_id); in hmac_ll_config_hw_key_id()
82 REG_WRITE(HMAC_SET_PARA_FINISH_REG, 1); in hmac_ll_config_finish()
116 REG_WRITE(HMAC_WR_MESSAGE_MEM + (i * REG_WIDTH), block[i]); in hmac_ll_write_block_512()
119 REG_WRITE(HMAC_SET_MESSAGE_ONE_REG, 1); in hmac_ll_write_block_512()
138 REG_WRITE(HMAC_SET_INVALIDATE_DS_REG, 1); in hmac_ll_clean()
[all …]
Dsha_ll.h24 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_start_block()
25 REG_WRITE(SHA_START_REG, 1); in sha_ll_start_block()
35 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_continue_block()
36 REG_WRITE(SHA_CONTINUE_REG, 1); in sha_ll_continue_block()
46 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_start_dma()
47 REG_WRITE(SHA_DMA_START_REG, 1); in sha_ll_start_dma()
57 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_continue_dma()
58 REG_WRITE(SHA_DMA_CONTINUE_REG, 1); in sha_ll_continue_dma()
81 REG_WRITE(SHA_DMA_BLOCK_NUM_REG, num_blocks); in sha_ll_set_block_num()
107 REG_WRITE(&reg_addr_buf[i], data_words[i]); in sha_ll_fill_text_block()
[all …]
Daes_ll.h45 REG_WRITE(AES_KEY_0_REG + i * 4, key_word); in aes_ll_write_key()
63 REG_WRITE(AES_MODE_REG, mode_reg_base + ((key_bytes / 8) - 2)); in aes_ll_set_mode()
77 REG_WRITE(AES_TEXT_IN_0_REG + i * 4, input_word); in aes_ll_write_block()
104 REG_WRITE(AES_TRIGGER_REG, 1); in aes_ll_start_transform()
128 REG_WRITE(AES_BLOCK_MODE_REG, mode); in aes_ll_set_block_mode()
139 REG_WRITE(AES_INC_SEL_REG, 0); in aes_ll_set_inc()
148 REG_WRITE(AES_DMA_EXIT_REG, 0); in aes_ll_dma_exit()
160 REG_WRITE(AES_BLOCK_NUM_REG, num_blocks); in aes_ll_set_num_blocks()
174 REG_WRITE(&reg_addr_buf[i], iv_word); in aes_ll_set_iv()
200 REG_WRITE(AES_DMA_ENABLE_REG, enable); in aes_ll_dma_enable()
[all …]
/hal_espressif-latest/components/hal/esp32c3/include/hal/
Dhmac_ll.h46 REG_WRITE(HMAC_SET_START_REG, 1); in hmac_ll_start()
59 REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_UP); in hmac_ll_config_output()
62 REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE); in hmac_ll_config_output()
65 REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG); in hmac_ll_config_output()
68 REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL); in hmac_ll_config_output()
80 REG_WRITE(HMAC_SET_PARA_KEY_REG, key_id); in hmac_ll_config_hw_key_id()
90 REG_WRITE(HMAC_SET_PARA_FINISH_REG, 1); in hmac_ll_config_finish()
124 REG_WRITE(HMAC_WDATA_BASE + (i * REG_WIDTH), block[i]); in hmac_ll_write_block_512()
127 REG_WRITE(HMAC_SET_MESSAGE_ONE_REG, 1); in hmac_ll_write_block_512()
146 REG_WRITE(HMAC_SET_INVALIDATE_DS_REG, 1); in hmac_ll_clean()
[all …]
Dsha_ll.h32 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_start_block()
33 REG_WRITE(SHA_START_REG, 1); in sha_ll_start_block()
43 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_continue_block()
44 REG_WRITE(SHA_CONTINUE_REG, 1); in sha_ll_continue_block()
54 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_start_dma()
55 REG_WRITE(SHA_DMA_START_REG, 1); in sha_ll_start_dma()
65 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_continue_dma()
66 REG_WRITE(SHA_DMA_CONTINUE_REG, 1); in sha_ll_continue_dma()
89 REG_WRITE(SHA_BLOCK_NUM_REG, num_blocks); in sha_ll_set_block_num()
115 REG_WRITE(&reg_addr_buf[i], data_words[i]); in sha_ll_fill_text_block()
[all …]
Daes_ll.h45 REG_WRITE(AES_KEY_BASE + i * 4, key_word); in aes_ll_write_key()
63 REG_WRITE(AES_MODE_REG, mode_reg_base + ((key_bytes / 8) - 2)); in aes_ll_set_mode()
77 REG_WRITE(AES_TEXT_IN_BASE + i * 4, input_word); in aes_ll_write_block()
104 REG_WRITE(AES_TRIGGER_REG, 1); in aes_ll_start_transform()
128 REG_WRITE(AES_BLOCK_MODE_REG, mode); in aes_ll_set_block_mode()
139 REG_WRITE(AES_INC_SEL_REG, 0); in aes_ll_set_inc()
148 REG_WRITE(AES_DMA_EXIT_REG, 0); in aes_ll_dma_exit()
160 REG_WRITE(AES_BLOCK_NUM_REG, num_blocks); in aes_ll_set_num_blocks()
174 REG_WRITE(&reg_addr_buf[i], iv_word); in aes_ll_set_iv()
200 REG_WRITE(AES_DMA_ENABLE_REG, enable); in aes_ll_dma_enable()
[all …]
Dspi_flash_encrypted_ll.h71 REG_WRITE(AES_XTS_DESTINATION_REG, type); in spi_flash_encrypt_ll_type()
82 REG_WRITE(AES_XTS_SIZE_REG, size >> 5); in spi_flash_encrypt_ll_buffer_length()
106 REG_WRITE(AES_XTS_PHYSICAL_ADDR_REG, flash_addr); in spi_flash_encrypt_ll_address_save()
114 REG_WRITE(AES_XTS_TRIGGER_REG, 1); in spi_flash_encrypt_ll_calculate_start()
131 REG_WRITE(AES_XTS_RELEASE_REG, 1); in spi_flash_encrypt_ll_done()
141 REG_WRITE(AES_XTS_DESTROY_REG, 1); in spi_flash_encrypt_ll_destroy()
/hal_espressif-latest/components/hal/esp32h2/include/hal/
Dhmac_ll.h38 REG_WRITE(HMAC_SET_START_REG, 1); in hmac_ll_start()
51 REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_UP); in hmac_ll_config_output()
54 REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE); in hmac_ll_config_output()
57 REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG); in hmac_ll_config_output()
60 REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL); in hmac_ll_config_output()
72 REG_WRITE(HMAC_SET_PARA_KEY_REG, key_id); in hmac_ll_config_hw_key_id()
82 REG_WRITE(HMAC_SET_PARA_FINISH_REG, 1); in hmac_ll_config_finish()
116 REG_WRITE(HMAC_WR_MESSAGE_MEM + (i * REG_WIDTH), block[i]); in hmac_ll_write_block_512()
119 REG_WRITE(HMAC_SET_MESSAGE_ONE_REG, 1); in hmac_ll_write_block_512()
138 REG_WRITE(HMAC_SET_INVALIDATE_DS_REG, 1); in hmac_ll_clean()
[all …]
Dsha_ll.h24 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_start_block()
25 REG_WRITE(SHA_START_REG, 1); in sha_ll_start_block()
35 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_continue_block()
36 REG_WRITE(SHA_CONTINUE_REG, 1); in sha_ll_continue_block()
46 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_start_dma()
47 REG_WRITE(SHA_DMA_START_REG, 1); in sha_ll_start_dma()
57 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_continue_dma()
58 REG_WRITE(SHA_DMA_CONTINUE_REG, 1); in sha_ll_continue_dma()
81 REG_WRITE(SHA_DMA_BLOCK_NUM_REG, num_blocks); in sha_ll_set_block_num()
107 REG_WRITE(&reg_addr_buf[i], data_words[i]); in sha_ll_fill_text_block()
[all …]
Daes_ll.h45 REG_WRITE(AES_KEY_0_REG + i * 4, key_word); in aes_ll_write_key()
63 REG_WRITE(AES_MODE_REG, mode_reg_base + ((key_bytes / 8) - 2)); in aes_ll_set_mode()
77 REG_WRITE(AES_TEXT_IN_0_REG + i * 4, input_word); in aes_ll_write_block()
104 REG_WRITE(AES_TRIGGER_REG, 1); in aes_ll_start_transform()
128 REG_WRITE(AES_BLOCK_MODE_REG, mode); in aes_ll_set_block_mode()
139 REG_WRITE(AES_INC_SEL_REG, 0); in aes_ll_set_inc()
148 REG_WRITE(AES_DMA_EXIT_REG, 0); in aes_ll_dma_exit()
160 REG_WRITE(AES_BLOCK_NUM_REG, num_blocks); in aes_ll_set_num_blocks()
174 REG_WRITE(&reg_addr_buf[i], iv_word); in aes_ll_set_iv()
200 REG_WRITE(AES_DMA_ENABLE_REG, enable); in aes_ll_dma_enable()
[all …]
/hal_espressif-latest/components/hal/esp32s2/include/hal/
Dsha_ll.h33 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_start_block()
34 REG_WRITE(SHA_START_REG, 1); in sha_ll_start_block()
44 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_continue_block()
45 REG_WRITE(SHA_CONTINUE_REG, 1); in sha_ll_continue_block()
55 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_start_dma()
56 REG_WRITE(SHA_DMA_START_REG, 1); in sha_ll_start_dma()
66 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_continue_dma()
67 REG_WRITE(SHA_DMA_CONTINUE_REG, 1); in sha_ll_continue_dma()
90 REG_WRITE(SHA_BLOCK_NUM_REG, num_blocks); in sha_ll_set_block_num()
116 REG_WRITE(&reg_addr_buf[i], data_words[i]); in sha_ll_fill_text_block()
[all …]
Daes_ll.h46 REG_WRITE(AES_KEY_BASE + i * 4, key_word); in aes_ll_write_key()
64 REG_WRITE(AES_MODE_REG, mode_reg_base + ((key_bytes / 8) - 2)); in aes_ll_set_mode()
78 REG_WRITE(AES_TEXT_IN_BASE + i * 4, input_word); in aes_ll_write_block()
106 REG_WRITE(AES_TRIGGER_REG, 1); in aes_ll_start_transform()
116 REG_WRITE(AES_CONTINUE_REG, 1); in aes_ll_cont_transform()
139 REG_WRITE(AES_BLOCK_MODE_REG, mode); in aes_ll_set_block_mode()
150 REG_WRITE(AES_INC_SEL_REG, 0); in aes_ll_set_inc()
159 REG_WRITE(AES_DMA_EXIT_REG, 0); in aes_ll_dma_exit()
171 REG_WRITE(AES_BLOCK_NUM_REG, num_blocks); in aes_ll_set_num_blocks()
185 REG_WRITE(&reg_addr_buf[i], iv_word); in aes_ll_set_iv()
[all …]
Dspi_flash_encrypted_ll.h81 REG_WRITE(AES_XTS_DESTINATION_REG, type); in spi_flash_encrypt_ll_type()
92 REG_WRITE(AES_XTS_SIZE_REG, size >> 5); in spi_flash_encrypt_ll_buffer_length()
115 REG_WRITE(AES_XTS_PHYSICAL_ADDR_REG, flash_addr); in spi_flash_encrypt_ll_address_save()
123 REG_WRITE(AES_XTS_TRIGGER_REG, 1); in spi_flash_encrypt_ll_calculate_start()
140 REG_WRITE(AES_XTS_RELEASE_REG, 1); in spi_flash_encrypt_ll_done()
150 REG_WRITE(AES_XTS_DESTROY_REG, 1); in spi_flash_encrypt_ll_destroy()
/hal_espressif-latest/components/mbedtls/port/esp32c3/
Dbignum.c40 REG_WRITE(RSA_INTERRUPT_REG, 0); in esp_mpi_enable_hardware_hw_op()
55 REG_WRITE(RSA_INTERRUPT_REG, enable); in esp_mpi_interrupt_enable()
60 REG_WRITE(RSA_CLEAR_INTERRUPT_REG, 1); in esp_mpi_interrupt_clear()
111 REG_WRITE(RSA_CLEAR_INTERRUPT_REG, 1); in start_op()
116 REG_WRITE(op_reg, 1); in start_op()
127 REG_WRITE(RSA_CLEAR_INTERRUPT_REG, 1); in wait_op_complete()
145 REG_WRITE(RSA_LENGTH_REG, (num_words - 1)); in esp_mpi_mul_mpi_mod_hw_op()
152 REG_WRITE(RSA_M_DASH_REG, Mprime); in esp_mpi_mul_mpi_mod_hw_op()
163 REG_WRITE(RSA_LENGTH_REG, (num_words - 1)); in esp_mpi_exp_mpi_mod_hw_op()
170 REG_WRITE(RSA_M_DASH_REG, Mprime); in esp_mpi_exp_mpi_mod_hw_op()
[all …]
/hal_espressif-latest/components/mbedtls/port/esp32c6/
Dbignum.c41 REG_WRITE(RSA_INT_ENA_REG, 0); in esp_mpi_enable_hardware_hw_op()
56 REG_WRITE(RSA_INT_ENA_REG, enable); in esp_mpi_interrupt_enable()
61 REG_WRITE(RSA_INT_CLR_REG, 1); in esp_mpi_interrupt_clear()
112 REG_WRITE(RSA_INT_CLR_REG, 1); in start_op()
117 REG_WRITE(op_reg, 1); in start_op()
128 REG_WRITE(RSA_INT_CLR_REG, 1); in wait_op_complete()
146 REG_WRITE(RSA_MODE_REG, (num_words - 1)); in esp_mpi_mul_mpi_mod_hw_op()
153 REG_WRITE(RSA_M_PRIME_REG, Mprime); in esp_mpi_mul_mpi_mod_hw_op()
164 REG_WRITE(RSA_MODE_REG, (num_words - 1)); in esp_mpi_exp_mpi_mod_hw_op()
171 REG_WRITE(RSA_M_PRIME_REG, Mprime); in esp_mpi_exp_mpi_mod_hw_op()
[all …]
/hal_espressif-latest/components/mbedtls/port/esp32h2/
Dbignum.c41 REG_WRITE(RSA_INT_ENA_REG, 0); in esp_mpi_enable_hardware_hw_op()
56 REG_WRITE(RSA_INT_ENA_REG, enable); in esp_mpi_interrupt_enable()
61 REG_WRITE(RSA_INT_CLR_REG, 1); in esp_mpi_interrupt_clear()
112 REG_WRITE(RSA_INT_CLR_REG, 1); in start_op()
117 REG_WRITE(op_reg, 1); in start_op()
128 REG_WRITE(RSA_INT_CLR_REG, 1); in wait_op_complete()
146 REG_WRITE(RSA_MODE_REG, (num_words - 1)); in esp_mpi_mul_mpi_mod_hw_op()
153 REG_WRITE(RSA_M_PRIME_REG, Mprime); in esp_mpi_mul_mpi_mod_hw_op()
164 REG_WRITE(RSA_MODE_REG, (num_words - 1)); in esp_mpi_exp_mpi_mod_hw_op()
171 REG_WRITE(RSA_M_PRIME_REG, Mprime); in esp_mpi_exp_mpi_mod_hw_op()
[all …]
/hal_espressif-latest/components/hal/esp32c2/include/hal/
Dsha_ll.h24 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_start_block()
25 REG_WRITE(SHA_START_REG, 1); in sha_ll_start_block()
35 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_continue_block()
36 REG_WRITE(SHA_CONTINUE_REG, 1); in sha_ll_continue_block()
46 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_start_dma()
47 REG_WRITE(SHA_DMA_START_REG, 1); in sha_ll_start_dma()
57 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_continue_dma()
58 REG_WRITE(SHA_DMA_CONTINUE_REG, 1); in sha_ll_continue_dma()
81 REG_WRITE(SHA_BLOCK_NUM_REG, num_blocks); in sha_ll_set_block_num()
107 REG_WRITE(&reg_addr_buf[i], data_words[i]); in sha_ll_fill_text_block()
[all …]
Dspi_flash_encrypted_ll.h63 REG_WRITE(AES_XTS_DESTINATION_REG, type); in spi_flash_encrypt_ll_type()
74 REG_WRITE(AES_XTS_SIZE_REG, size >> 5); in spi_flash_encrypt_ll_buffer_length()
98 REG_WRITE(AES_XTS_PHYSICAL_ADDR_REG, flash_addr); in spi_flash_encrypt_ll_address_save()
106 REG_WRITE(AES_XTS_TRIGGER_REG, 1); in spi_flash_encrypt_ll_calculate_start()
123 REG_WRITE(AES_XTS_RELEASE_REG, 1); in spi_flash_encrypt_ll_done()
133 REG_WRITE(AES_XTS_DESTROY_REG, 1); in spi_flash_encrypt_ll_destroy()
/hal_espressif-latest/components/esp_timer/src/
Desp_timer_impl_lac.c119 REG_WRITE(UPDATE_REG, 1); in esp_timer_impl_get_counter_reg()
160 REG_WRITE(ALARM_LO_REG, alarm.lo); in esp_timer_impl_set_alarm_id()
161 REG_WRITE(ALARM_HI_REG, alarm.hi); in esp_timer_impl_set_alarm_id()
181 REG_WRITE(INT_CLR_REG, TIMG_LACT_INT_CLR); in timer_alarm_isr()
199 REG_WRITE(LOAD_LO_REG, dst.lo); in esp_timer_impl_set()
200 REG_WRITE(LOAD_HI_REG, dst.hi); in esp_timer_impl_set()
201 REG_WRITE(LOAD_REG, 1); in esp_timer_impl_set()
215 REG_WRITE(CONFIG_REG, 0); in esp_timer_impl_early_init()
216 REG_WRITE(LOAD_LO_REG, 0); in esp_timer_impl_early_init()
217 REG_WRITE(LOAD_HI_REG, 0); in esp_timer_impl_early_init()
[all …]
/hal_espressif-latest/components/esp_rom/patches/
Desp_rom_regi2c_esp32h2.c95 REG_WRITE(I2C_MST_ANA_CONF1_REG, REGI2C_BBPLL_RD_MASK); in regi2c_enable_block()
99 REG_WRITE(I2C_MST_ANA_CONF1_REG, REGI2C_BIAS_RD_MASK); in regi2c_enable_block()
103 REG_WRITE(I2C_MST_ANA_CONF1_REG, REGI2C_DIG_REG_RD_MASK); in regi2c_enable_block()
107 REG_WRITE(I2C_MST_ANA_CONF1_REG, REGI2C_ULP_CAL_RD_MASK); in regi2c_enable_block()
111 REG_WRITE(I2C_MST_ANA_CONF1_REG, REGI2C_SAR_I2C_RD_MASK); in regi2c_enable_block()
126 REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); in regi2c_read_impl()
142 REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); in regi2c_read_mask_impl()
160 REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); in regi2c_write_impl()
175 REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); in regi2c_write_mask_impl()
185 REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); in regi2c_write_mask_impl()
Desp_rom_hp_regi2c_esp32c6.c96 REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_BBPLL_RD_MASK); in regi2c_enable_block()
100 REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_BIAS_RD_MASK); in regi2c_enable_block()
104 REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_DIG_REG_RD_MASK); in regi2c_enable_block()
108 REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_ULP_CAL_RD_MASK); in regi2c_enable_block()
112 REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_SAR_I2C_RD_MASK); in regi2c_enable_block()
127 REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); in regi2c_read_impl()
143 REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); in regi2c_read_mask_impl()
161 REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); in regi2c_write_impl()
176 REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); in regi2c_write_mask_impl()
186 REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); in regi2c_write_mask_impl()

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