Home
last modified time | relevance | path

Searched refs:REG_TIMG_BASE (Results 1 – 15 of 15) sorted by relevance

/hal_espressif-latest/components/soc/esp32/include/soc/
Dtimer_group_reg.h34 #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + i*0x1000) macro
35 #define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0000)
80 #define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x0004)
88 #define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x0008)
96 #define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x000c)
105 #define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0010)
113 #define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0014)
121 #define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x0018)
129 #define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x001c)
137 #define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x0020)
[all …]
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Dtimer_group_reg.h26 #define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0)
76 #define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x4)
89 #define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x8)
102 #define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0xc)
114 #define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x10)
126 #define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x14)
138 #define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x18)
151 #define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x1c)
164 #define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x20)
177 #define TIMG_T1CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x24)
[all …]
Dsoc.h35 #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) macro
/hal_espressif-latest/components/soc/esp32c6/include/soc/
Dtimer_group_reg.h41 #define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0)
98 #define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x4)
111 #define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x8)
124 #define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0xc)
136 #define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x10)
148 #define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x14)
160 #define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x18)
173 #define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x1c)
186 #define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x20)
199 #define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x48)
[all …]
Dsoc.h24 #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) // TIMERG0… macro
/hal_espressif-latest/components/soc/esp32h2/include/soc/
Dtimer_group_reg.h41 #define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0)
98 #define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x4)
111 #define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x8)
124 #define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0xc)
136 #define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x10)
148 #define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x14)
160 #define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x18)
173 #define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x1c)
186 #define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x20)
199 #define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x48)
[all …]
Dsoc.h24 #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) macro
/hal_espressif-latest/components/esp_hw_support/
Dsleep_system_peripheral.c106 #define N_REGS_TG() (((TIMG_REGCLK_REG(0) - REG_TIMG_BASE(0)) / 4) + 1) in sleep_sys_periph_tg0_retention_init()
111 …ig = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TIMG_LINK(0x01), REG_TIMG_BASE(0), REG_TIMG_BASE(0)… in sleep_sys_periph_tg0_retention_init()
/hal_espressif-latest/components/soc/esp32c2/include/soc/
Dsoc.h32 #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) macro
Dtimer_group_reg.h14 #define DR_REG_TIMG_BASE(i) REG_TIMG_BASE(i)
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Dsoc.h26 #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) macro
Dtimer_group_reg.h14 #define DR_REG_TIMG_BASE(i) REG_TIMG_BASE(i)
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Dsoc.h24 #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) macro
Dtimer_group_reg.h14 #define DR_REG_TIMG_BASE(i) REG_TIMG_BASE(i)
/hal_espressif-latest/components/esp_system/port/soc/esp32/
Dhighint_hdl.S66 #define TIMG1_REG_OFFSET(reg) ((reg) - REG_TIMG_BASE(1))