Searched refs:REG_SPI_MEM_BASE (Results 1 – 15 of 15) sorted by relevance
14 #define XTS_AES_PLAIN_MEM(i) (REG_SPI_MEM_BASE(i) + 0x300)23 #define XTS_AES_LINESIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x340)33 #define XTS_AES_DESTINATION_REG(i) (REG_SPI_MEM_BASE(i) + 0x344)43 #define XTS_AES_PHYSICAL_ADDRESS_REG(i) (REG_SPI_MEM_BASE(i) + 0x348)53 #define XTS_AES_TRIGGER_REG(i) (REG_SPI_MEM_BASE(i) + 0x34C)64 #define XTS_AES_RELEASE_REG(i) (REG_SPI_MEM_BASE(i) + 0x350)74 #define XTS_AES_DESTROY_REG(i) (REG_SPI_MEM_BASE(i) + 0x354)84 #define XTS_AES_STATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x358)94 #define XTS_AES_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x35C)101 #define XTS_AES_DPA_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x388)
19 #define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x0)147 #define SPI_MEM_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x4)156 #define SPI_MEM_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x8)311 #define SPI_MEM_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0xC)406 #define SPI_MEM_CTRL2_REG(i) (REG_SPI_MEM_BASE(i) + 0x10)465 #define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x14)493 #define SPI_MEM_USER_REG(i) (REG_SPI_MEM_BASE(i) + 0x18)587 #define SPI_MEM_USER1_REG(i) (REG_SPI_MEM_BASE(i) + 0x1C)608 #define SPI_MEM_USER2_REG(i) (REG_SPI_MEM_BASE(i) + 0x20)622 #define SPI_MEM_MOSI_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x24)[all …]
25 #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE + (i) * 0x1000) // SPIMEM0… macro
14 #define XTS_AES_PLAIN_MEM(i) (REG_SPI_MEM_BASE(i) + 0x300)23 #define XTS_AES_LINESIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x340)33 #define XTS_AES_DESTINATION_REG(i) (REG_SPI_MEM_BASE(i) + 0x344)43 #define XTS_AES_PHYSICAL_ADDRESS_REG(i) (REG_SPI_MEM_BASE(i) + 0x348)53 #define XTS_AES_TRIGGER_REG(i) (REG_SPI_MEM_BASE(i) + 0x34C)64 #define XTS_AES_RELEASE_REG(i) (REG_SPI_MEM_BASE(i) + 0x350)74 #define XTS_AES_DESTROY_REG(i) (REG_SPI_MEM_BASE(i) + 0x354)84 #define XTS_AES_STATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x358)94 #define XTS_AES_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x35C)102 #define XTS_AES_DPA_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x388)
14 #define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x0)142 #define SPI_MEM_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x4)151 #define SPI_MEM_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x8)306 #define SPI_MEM_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0xC)401 #define SPI_MEM_CTRL2_REG(i) (REG_SPI_MEM_BASE(i) + 0x10)460 #define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x14)488 #define SPI_MEM_USER_REG(i) (REG_SPI_MEM_BASE(i) + 0x18)582 #define SPI_MEM_USER1_REG(i) (REG_SPI_MEM_BASE(i) + 0x1C)603 #define SPI_MEM_USER2_REG(i) (REG_SPI_MEM_BASE(i) + 0x20)617 #define SPI_MEM_MOSI_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x24)[all …]
25 #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE + (i) * 0x1000) macro
15 #define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x0)140 #define SPI_MEM_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x4)149 #define SPI_MEM_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x8)248 #define SPI_MEM_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0xC)271 #define SPI_MEM_CTRL2_REG(i) (REG_SPI_MEM_BASE(i) + 0x10)301 #define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x14)328 #define SPI_MEM_USER_REG(i) (REG_SPI_MEM_BASE(i) + 0x18)423 #define SPI_MEM_USER1_REG(i) (REG_SPI_MEM_BASE(i) + 0x1C)438 #define SPI_MEM_USER2_REG(i) (REG_SPI_MEM_BASE(i) + 0x20)452 #define SPI_MEM_MOSI_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x24)[all …]
33 #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) macro
22 #define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x000)142 #define SPI_MEM_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x004)151 #define SPI_MEM_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x008)250 #define SPI_MEM_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0x00C)279 #define SPI_MEM_CTRL2_REG(i) (REG_SPI_MEM_BASE(i) + 0x010)308 #define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x014)335 #define SPI_MEM_USER_REG(i) (REG_SPI_MEM_BASE(i) + 0x018)430 #define SPI_MEM_USER1_REG(i) (REG_SPI_MEM_BASE(i) + 0x01C)445 #define SPI_MEM_USER2_REG(i) (REG_SPI_MEM_BASE(i) + 0x020)459 #define SPI_MEM_MOSI_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x024)[all …]
25 #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) macro
15 #define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x000)122 #define SPI_MEM_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x004)131 #define SPI_MEM_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x008)254 #define SPI_MEM_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0x00C)295 #define SPI_MEM_CTRL2_REG(i) (REG_SPI_MEM_BASE(i) + 0x010)317 #define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x014)344 #define SPI_MEM_USER_REG(i) (REG_SPI_MEM_BASE(i) + 0x018)439 #define SPI_MEM_USER1_REG(i) (REG_SPI_MEM_BASE(i) + 0x01C)454 #define SPI_MEM_USER2_REG(i) (REG_SPI_MEM_BASE(i) + 0x020)468 #define SPI_MEM_MOSI_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x024)[all …]
27 #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) macro
23 #define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x0)134 #define SPI_MEM_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x4)143 #define SPI_MEM_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x8)268 #define SPI_MEM_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0xC)292 #define SPI_MEM_CTRL2_REG(i) (REG_SPI_MEM_BASE(i) + 0x10)344 #define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x14)372 #define SPI_MEM_USER_REG(i) (REG_SPI_MEM_BASE(i) + 0x18)468 #define SPI_MEM_USER1_REG(i) (REG_SPI_MEM_BASE(i) + 0x1C)482 #define SPI_MEM_USER2_REG(i) (REG_SPI_MEM_BASE(i) + 0x20)496 #define SPI_MEM_MOSI_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x24)[all …]
36 #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) macro
154 #define N_REGS_SPI1_MEM_0() (((SPI_MEM_SPI_SMEM_DDR_REG(1) - REG_SPI_MEM_BASE(1)) / 4) + 1) in sleep_sys_periph_spimem_retention_init()159 #define N_REGS_SPI0_MEM_0() (((SPI_MEM_SPI_SMEM_DDR_REG(0) - REG_SPI_MEM_BASE(0)) / 4) + 1) in sleep_sys_periph_spimem_retention_init()166 …DMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x00), REG_SPI_MEM_BASE(1), REG_SPI_MEM_… in sleep_sys_periph_spimem_retention_init()172 …DMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x04), REG_SPI_MEM_BASE(0), REG_SPI_MEM_… in sleep_sys_periph_spimem_retention_init()
