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Searched refs:REG_GET_BIT (Results 1 – 25 of 33) sorted by relevance

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/hal_espressif-latest/components/esp_rom/patches/
Desp_rom_regi2c_esp32h2.c94 i2c_sel = REG_GET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_BBPLL_MST_SEL); in regi2c_enable_block()
98 i2c_sel = REG_GET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_BIAS_MST_SEL); in regi2c_enable_block()
102 i2c_sel = REG_GET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_DIG_REG_MST_SEL); in regi2c_enable_block()
106 i2c_sel = REG_GET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_ULP_CAL_MST_SEL); in regi2c_enable_block()
110 i2c_sel = REG_GET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_SAR_I2C_MST_SEL); in regi2c_enable_block()
123 while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle in regi2c_read_impl()
127 while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); in regi2c_read_impl()
139 while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle in regi2c_read_mask_impl()
143 while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); in regi2c_read_mask_impl()
155 while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle in regi2c_write_impl()
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Desp_rom_hp_regi2c_esp32c6.c95 i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BBPLL_MST_SEL); in regi2c_enable_block()
99 i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BIAS_MST_SEL); in regi2c_enable_block()
103 i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_DIG_REG_MST_SEL); in regi2c_enable_block()
107 i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_ULP_CAL_MST_SEL); in regi2c_enable_block()
111 i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_SAR_I2C_MST_SEL); in regi2c_enable_block()
124 while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle in regi2c_read_impl()
128 while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); in regi2c_read_impl()
140 while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle in regi2c_read_mask_impl()
144 while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); in regi2c_read_mask_impl()
156 while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle in regi2c_write_impl()
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Desp_rom_regi2c_esp32s2.c118 while (REG_GET_BIT(I2C_RTC_CONFIG2, I2C_RTC_BUSY)); in esp_rom_regi2c_read()
130 while (REG_GET_BIT(I2C_RTC_CONFIG2, I2C_RTC_BUSY)); in esp_rom_regi2c_read_mask()
144 while (REG_GET_BIT(I2C_RTC_CONFIG2, I2C_RTC_BUSY)); in esp_rom_regi2c_write()
156 while (REG_GET_BIT(I2C_RTC_CONFIG2, I2C_RTC_BUSY)); in esp_rom_regi2c_write_mask()
166 while (REG_GET_BIT(I2C_RTC_CONFIG2, I2C_RTC_BUSY)); in esp_rom_regi2c_write_mask()
/hal_espressif-latest/components/hal/esp32s3/include/hal/
Dmemprot_ll.h429 …HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONIT… in memprot_ll_iram0_set_monitor_en()
434 …HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONIT… in memprot_ll_iram0_set_monitor_en()
442 …HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONIT… in memprot_ll_iram0_set_monitor_en()
447 …HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONIT… in memprot_ll_iram0_set_monitor_en()
480 …HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONIT… in memprot_ll_iram0_set_monitor_intrclr()
486 …HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONIT… in memprot_ll_iram0_set_monitor_intrclr()
502 …HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONIT… in memprot_ll_iram0_reset_monitor_intrclr()
508 …HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONIT… in memprot_ll_iram0_reset_monitor_intrclr()
522 …*cleared = REG_GET_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITO… in memprot_ll_iram0_get_monitor_intrclr()
525 …*cleared = REG_GET_BIT(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITO… in memprot_ll_iram0_get_monitor_intrclr()
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Dcache_ll.h55 enabled = REG_GET_BIT(EXTMEM_ICACHE_CTRL_REG, EXTMEM_ICACHE_ENABLE); in cache_ll_l1_is_cache_enabled()
57 enabled = REG_GET_BIT(EXTMEM_DCACHE_CTRL_REG, EXTMEM_DCACHE_ENABLE); in cache_ll_l1_is_cache_enabled()
59 enabled = REG_GET_BIT(EXTMEM_ICACHE_CTRL_REG, EXTMEM_ICACHE_ENABLE); in cache_ll_l1_is_cache_enabled()
60 enabled = enabled && REG_GET_BIT(EXTMEM_DCACHE_CTRL_REG, EXTMEM_DCACHE_ENABLE); in cache_ll_l1_is_cache_enabled()
Dregi2c_ctrl_ll.h76 return REG_GET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE); in regi2c_ctrl_ll_bbpll_calibration_is_done()
Dmspi_timing_tuning_ll.h369 return REG_GET_BIT(SPI_MEM_USER_REG(spi_num), SPI_MEM_CS_SETUP); in mspi_timing_ll_is_cs_setup_enabled()
396 return REG_GET_BIT(SPI_MEM_USER_REG(spi_num), SPI_MEM_CS_HOLD); in mspi_timing_ll_is_cs_hold_enabled()
/hal_espressif-latest/components/hal/esp32s2/include/hal/
Dcache_ll.h39 enabled = REG_GET_BIT(EXTMEM_PRO_ICACHE_CTRL_REG, EXTMEM_PRO_ICACHE_ENABLE); in cache_ll_l1_is_cache_enabled()
41 enabled = REG_GET_BIT(EXTMEM_PRO_DCACHE_CTRL_REG, EXTMEM_PRO_DCACHE_ENABLE); in cache_ll_l1_is_cache_enabled()
43 enabled = REG_GET_BIT(EXTMEM_PRO_ICACHE_CTRL_REG, EXTMEM_PRO_ICACHE_ENABLE); in cache_ll_l1_is_cache_enabled()
44 enabled = enabled && REG_GET_BIT(EXTMEM_PRO_DCACHE_CTRL_REG, EXTMEM_PRO_DCACHE_ENABLE); in cache_ll_l1_is_cache_enabled()
/hal_espressif-latest/components/hal/esp32/include/hal/
Dgpio_ll.h107 return REG_GET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU) ? true : false; in gpio_ll_pullup_is_enabled()
142 return REG_GET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD) ? true : false; in gpio_ll_pulldown_is_enabled()
176 return REG_GET_BIT(GPIO_PIN_MUX_REG[gpio_num], SLP_SEL) ? true : false; in gpio_ll_sleep_sel_is_enabled()
210 return REG_GET_BIT(GPIO_PIN_MUX_REG[gpio_num], SLP_PU) ? true : false; in gpio_ll_sleep_pullup_is_enabled()
244 return REG_GET_BIT(GPIO_PIN_MUX_REG[gpio_num], SLP_PD) ? true : false; in gpio_ll_sleep_pulldown_is_enabled()
/hal_espressif-latest/components/esp_hw_support/
Drtc_wdt.c150 …return (REG_GET_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_EN) != 0) || (REG_GET_BIT(RTC_CNTL_WDTCO… in rtc_wdt_is_on()
/hal_espressif-latest/components/hal/esp32h2/include/hal/
Decdsa_ll.h273 return REG_GET_BIT(ECDSA_SHA_BUSY_REG, ECDSA_SHA_BUSY); in ecdsa_ll_sha_is_busy()
356 return REG_GET_BIT(ECDSA_RESULT_REG, ECDSA_OPERATION_RESULT); in ecdsa_ll_get_operation_result()
Dregi2c_ctrl_ll.h45 return REG_GET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE); in regi2c_ctrl_ll_bbpll_calibration_is_done()
Dclk_gate_ll.h368 …return REG_GET_BIT(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)) == … in periph_ll_periph_enabled()
369 REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0; in periph_ll_periph_enabled()
/hal_espressif-latest/components/hal/esp32c6/include/hal/
Dregi2c_ctrl_ll.h43 return REG_GET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE); in regi2c_ctrl_ll_bbpll_calibration_is_done()
Dlp_aon_ll.h95 return REG_GET_BIT(LP_AON_LPCORE_REG, LP_AON_LPCORE_ETM_WAKEUP_FLAG); in lp_aon_ll_get_lpcore_etm_wakeup_flag()
Dclk_gate_ll.h367 (REG_GET_BIT(clk_en_reg, periph_ll_get_clk_en_mask(periph)) != 0); in periph_ll_periph_enabled()
370 (REG_GET_BIT(rst_en_reg, periph_ll_get_rst_en_mask(periph, false)) == 0); in periph_ll_periph_enabled()
/hal_espressif-latest/components/hal/esp32c2/include/hal/
Dregi2c_ctrl_ll.h58 return REG_GET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE); in regi2c_ctrl_ll_bbpll_calibration_is_done()
Dcache_ll.h50 return REG_GET_BIT(EXTMEM_ICACHE_CTRL_REG, EXTMEM_ICACHE_ENABLE); in cache_ll_l1_is_cache_enabled()
/hal_espressif-latest/components/hal/esp32c3/include/hal/
Dmemprot_ll.h256 …return REG_GET_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VI… in memprot_ll_iram0_get_monitor_intrclr()
546 …return REG_GET_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLAT… in memprot_ll_rtcfast_get_monitor_intrclr()
776 …return REG_GET_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VI… in memprot_ll_dram0_get_monitor_en()
791 …return REG_GET_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VI… in memprot_ll_dram0_get_monitor_intrclr()
Dcache_ll.h51 return REG_GET_BIT(EXTMEM_ICACHE_CTRL_REG, EXTMEM_ICACHE_ENABLE); in cache_ll_l1_is_cache_enabled()
/hal_espressif-latest/components/spi_flash/
Dspi_flash_wrap.c156 if (!REG_GET_BIT(SPI_MEM_CTRL_REG(0), SPI_MEM_FREAD_QIO)) { in spi_flash_support_wrap_size()
/hal_espressif-latest/components/soc/esp32/include/soc/
Dsoc.h52 #define REG_GET_BIT(_r, _b) ({ … macro
53 …ASSERT_IF_DPORT_REG((_r), REG_GET_BIT); …
/hal_espressif-latest/components/riscv/include/riscv/
Drv_utils.h203 return REG_GET_BIT(ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG, ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE); in rv_utils_dbgr_is_attached()
/hal_espressif-latest/components/soc/esp32c2/include/soc/
Dsoc.h54 #define REG_GET_BIT(_r, _b) ({ … macro
/hal_espressif-latest/components/soc/esp32c6/include/soc/
Dsoc.h48 #define REG_GET_BIT(_r, _b) ({ … macro

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