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Searched refs:REGI2C_WRITE_MASK (Results 1 – 25 of 55) sorted by relevance

123

/hal_espressif-latest/components/bootloader_support/src/
Dbootloader_random_esp32c6.c44 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR , 2); in bootloader_random_enable()
45 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR , 1); in bootloader_random_enable()
46 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 1); in bootloader_random_enable()
47 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 1); in bootloader_random_enable()
49 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, 0x08); in bootloader_random_enable()
50 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, 0x66); in bootloader_random_enable()
51 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, 0x08); in bootloader_random_enable()
52 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, 0x66); in bootloader_random_enable()
82 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, 0x60); in bootloader_random_disable()
83 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, 0x0); in bootloader_random_disable()
[all …]
Dbootloader_random_esp32h2.c38 REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_DTEST, 0); in bootloader_random_enable()
39 REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_ENT_SAR, 1); in bootloader_random_enable()
40 REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_EN_TOUT_SAR1_BUS, 1); in bootloader_random_enable()
42 REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR2_INIT_CODE_MSB, 0X08); in bootloader_random_enable()
43 REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR2_INIT_CODE_LSB, 0X66); in bootloader_random_enable()
44 REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR1_INIT_CODE_MSB, 0X08); in bootloader_random_enable()
45 REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR1_INIT_CODE_LSB, 0X66); in bootloader_random_enable()
75 REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR2_INIT_CODE_MSB, 0x60); in bootloader_random_disable()
76 REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR2_INIT_CODE_LSB, 0x0); in bootloader_random_disable()
77 REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR1_INIT_CODE_MSB, 0x60); in bootloader_random_disable()
[all …]
Dbootloader_random_esp32s2.c48 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 0x4); in bootloader_random_enable()
49 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_DREF_ADDR, 0x4); in bootloader_random_enable()
51 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENCAL_REF_ADDR, 1); in bootloader_random_enable()
52 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 1); in bootloader_random_enable()
53 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0); in bootloader_random_enable()
81 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 0x1); in bootloader_random_disable()
82 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_DREF_ADDR, 0x1); in bootloader_random_disable()
84 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENCAL_REF_ADDR, 0); in bootloader_random_disable()
85 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0); in bootloader_random_disable()
86 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0); in bootloader_random_disable()
Dbootloader_random_esp32s3.c71 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENCAL_REF_ADDR, 1); in bootloader_random_enable()
72 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 1); in bootloader_random_enable()
73 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0); in bootloader_random_enable()
74 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0); in bootloader_random_enable()
81 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENCAL_REF_ADDR, 0); in bootloader_random_disable()
82 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0); in bootloader_random_disable()
83 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0); in bootloader_random_disable()
84 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0); in bootloader_random_disable()
Dbootloader_random_esp32c2.c23 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 1); in bootloader_random_enable()
24 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0); in bootloader_random_enable()
25 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0); in bootloader_random_enable()
26 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0); in bootloader_random_enable()
57 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0); in bootloader_random_disable()
Dbootloader_random_esp32c3.c23 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 1); in bootloader_random_enable()
24 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0); in bootloader_random_enable()
25 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0); in bootloader_random_enable()
26 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0); in bootloader_random_enable()
57 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0); in bootloader_random_disable()
/hal_espressif-latest/zephyr/esp32c6/src/
Dsoc_random.c46 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 2); in soc_random_enable()
47 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 1); in soc_random_enable()
48 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 1); in soc_random_enable()
49 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 1); in soc_random_enable()
51 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, 0x08); in soc_random_enable()
52 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, 0x66); in soc_random_enable()
53 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, 0x08); in soc_random_enable()
54 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, 0x66); in soc_random_enable()
88 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, 0x60); in soc_random_disable()
89 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, 0x0); in soc_random_disable()
[all …]
/hal_espressif-latest/zephyr/esp32s2/src/
Dsoc_random.c43 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 0x4); in soc_random_enable()
44 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_DREF_ADDR, 0x4); in soc_random_enable()
46 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENCAL_REF_ADDR, 1); in soc_random_enable()
47 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 1); in soc_random_enable()
48 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0); in soc_random_enable()
76 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 0x1); in soc_random_disable()
77 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_DREF_ADDR, 0x1); in soc_random_disable()
79 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENCAL_REF_ADDR, 0); in soc_random_disable()
80 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0); in soc_random_disable()
81 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0); in soc_random_disable()
/hal_espressif-latest/zephyr/esp32s3/src/
Dsoc_random.c80 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENCAL_REF_ADDR, 1); in soc_random_enable()
81 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 1); in soc_random_enable()
82 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0); in soc_random_enable()
83 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0); in soc_random_enable()
89 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENCAL_REF_ADDR, 0); in soc_random_disable()
90 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0); in soc_random_disable()
91 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0); in soc_random_disable()
92 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0); in soc_random_disable()
/hal_espressif-latest/components/hal/esp32c3/include/hal/
Dadc_ll.h137 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_SAMPLE_CYCLE_ADDR, sample_cycle); in adc_ll_set_sample_cycle()
619 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 1); in adc_ll_calibration_init()
621 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_DREF_ADDR, 1); in adc_ll_calibration_init()
639 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 1); in adc_ll_calibration_prepare()
641 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0); in adc_ll_calibration_prepare()
645 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 1); in adc_ll_calibration_prepare()
647 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0); in adc_ll_calibration_prepare()
660 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0); in adc_ll_calibration_finish()
662 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0); in adc_ll_calibration_finish()
679 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb); in adc_ll_set_calibration_param()
[all …]
/hal_espressif-latest/zephyr/esp32c2/src/
Dsoc_random.c23 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 1); in soc_random_enable()
24 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0); in soc_random_enable()
25 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0); in soc_random_enable()
26 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0); in soc_random_enable()
58 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0); in soc_random_disable()
/hal_espressif-latest/zephyr/esp32c3/src/
Dsoc_random.c23 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 1); in soc_random_enable()
24 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0); in soc_random_enable()
25 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0); in soc_random_enable()
26 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0); in soc_random_enable()
58 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0); in soc_random_disable()
/hal_espressif-latest/components/hal/esp32s2/include/hal/
Dadc_ll.h160 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_SAMPLE_CYCLE_ADDR, sample_cycle); in adc_ll_set_sample_cycle()
1052 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 4); in adc_ll_calibration_init()
1054 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_DREF_ADDR, 4); in adc_ll_calibration_init()
1078 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 1); in adc_ll_calibration_prepare()
1080 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0); in adc_ll_calibration_prepare()
1084 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 1); in adc_ll_calibration_prepare()
1086 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0); in adc_ll_calibration_prepare()
1099 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0); in adc_ll_calibration_finish()
1101 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0); in adc_ll_calibration_finish()
1123 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb); in adc_ll_set_calibration_param()
[all …]
Dclk_tree_ll.h139 REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM2, sdm2); in clk_ll_apll_set_config()
140 REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM0, sdm0); in clk_ll_apll_set_config()
141 REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM1, sdm1); in clk_ll_apll_set_config()
144 REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_OR_OUTPUT_DIV, o_div); in clk_ll_apll_set_config()
423 REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR1, dr1); in clk_ll_bbpll_set_config()
424 REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3); in clk_ll_bbpll_set_config()
433 REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_IR_CAL_ENX_CAP, 1); in clk_ll_bbpll_calibration_enable()
445 REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP, ext_cap); in clk_ll_bbpll_calibration_is_done()
/hal_espressif-latest/components/esp_hw_support/port/esp32c6/
Docode_init.c26 REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_EXT_CODE, ocode); in set_ocode_by_efuse()
27 REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_CODE, 1); in set_ocode_by_efuse()
60 REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 0); in calibrate_ocode()
61 REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 1); in calibrate_ocode()
Drtc_clk_init.c75 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_SCK_DCAP, cfg.slow_clk_dcap); in rtc_clk_init()
77 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_RTC_DREG, 1); in rtc_clk_init()
78 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_DIG_DREG, 1); in rtc_clk_init()
/hal_espressif-latest/components/esp_hw_support/port/esp32c2/
Drtc_init.c34 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_DIG_REG, 0); in rtc_init()
35 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0); in rtc_init()
124 REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 1); in rtc_init()
142 REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_EXT_CODE, ocode); in set_ocode_by_efuse()
143 REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_CODE, 1); in set_ocode_by_efuse()
176 REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 0); in calibrate_ocode()
177 REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 1); in calibrate_ocode()
291 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, rtc_dbias); in set_rtc_dig_dbias()
292 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, dig_dbias); in set_rtc_dig_dbias()
/hal_espressif-latest/components/esp_hw_support/port/esp32c3/
Drtc_init.c45 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_DIG_REG, 0); in rtc_init()
46 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0); in rtc_init()
165 REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 1); in rtc_init()
178 REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_EXT_CODE, ocode); in set_ocode_by_efuse()
179 REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_CODE, 1); in set_ocode_by_efuse()
212 REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 0); in calibrate_ocode()
213 REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 1); in calibrate_ocode()
294 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, rtc_dbias); in set_rtc_dig_dbias()
295 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, dig_dbias); in set_rtc_dig_dbias()
/hal_espressif-latest/components/esp_hw_support/port/esp32s3/
Drtc_init.c59 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0); in rtc_init()
60 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_DIG_REG, 0); in rtc_init()
91 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, RTC_CNTL_DBIAS_1V10); in rtc_init()
92 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, RTC_CNTL_DBIAS_1V10); in rtc_init()
110 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, g_rtc_dbias_pvt_non_240m); in rtc_init()
111 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, g_dig_dbias_pvt_non_240m); in rtc_init()
255 REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_EXT_CODE, ocode); in set_ocode_by_efuse()
256 REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_CODE, 1); in set_ocode_by_efuse()
305 REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 0); in calibrate_ocode()
306 REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 1); in calibrate_ocode()
Drtc_clk.c207 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, g_rtc_dbias_pvt_240m); in rtc_clk_cpu_freq_to_pll_mhz()
208 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, g_dig_dbias_pvt_240m); in rtc_clk_cpu_freq_to_pll_mhz()
223 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, g_rtc_dbias_pvt_non_240m); in rtc_clk_cpu_freq_to_pll_mhz()
224 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, g_dig_dbias_pvt_non_240m); in rtc_clk_cpu_freq_to_pll_mhz()
394 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, g_rtc_dbias_pvt_non_240m); in rtc_clk_cpu_freq_to_xtal()
395 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, g_dig_dbias_pvt_non_240m); in rtc_clk_cpu_freq_to_xtal()
409 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, g_rtc_dbias_pvt_non_240m); in rtc_clk_cpu_freq_to_8m()
410 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, g_dig_dbias_pvt_non_240m); in rtc_clk_cpu_freq_to_8m()
/hal_espressif-latest/components/esp_hw_support/port/esp32h2/
Drtc_clk_init.c42 REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OC_SCK_DCAP, cfg.slow_clk_dcap); in rtc_clk_init()
44 REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_RTC_DREG, 0); in rtc_clk_init()
45 REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_DIG_DREG, 0); in rtc_clk_init()
Dpmu_init.c213 REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_RTC_DREG, 0); in pmu_init()
214 REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_DIG_DREG, 0); in pmu_init()
215 REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_RTC_DREG_SLP, 0); in pmu_init()
216 REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_DIG_DREG_SLP, 0); in pmu_init()
217 REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_XPD_RTC_REG, 0); in pmu_init()
218 REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_XPD_DIG_REG, 0); in pmu_init()
219 REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_XPD_TRX, 0); in pmu_init()
221 …REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_0P8, 8); // fix low temp issue, need to increase this i… in pmu_init()
/hal_espressif-latest/components/hal/esp32s3/include/hal/
Dadc_ll.h170 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_SAMPLE_CYCLE_ADDR, sample_cycle); in adc_ll_set_sample_cycle()
735 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 4); in adc_ll_calibration_init()
737 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_DREF_ADDR, 4); in adc_ll_calibration_init()
758 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 1); in adc_ll_calibration_prepare()
760 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0); in adc_ll_calibration_prepare()
764 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 1); in adc_ll_calibration_prepare()
766 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0); in adc_ll_calibration_prepare()
779 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0); in adc_ll_calibration_finish()
781 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0); in adc_ll_calibration_finish()
798 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb); in adc_ll_set_calibration_param()
[all …]
Dclk_tree_ll.h379 REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR1, dr1); in clk_ll_bbpll_set_config()
380 REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3); in clk_ll_bbpll_set_config()
382 REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_VCO_DBIAS, dbias); in clk_ll_bbpll_set_config()
713 REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR1, dr1); in clk_ll_bbpll_set_frequency_for_mspi_tuning()
714 REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3); in clk_ll_bbpll_set_frequency_for_mspi_tuning()
716 REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_VCO_DBIAS, dbias); in clk_ll_bbpll_set_frequency_for_mspi_tuning()
717 REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DHREF_SEL, 3); in clk_ll_bbpll_set_frequency_for_mspi_tuning()
718 REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DLREF_SEL, 1); in clk_ll_bbpll_set_frequency_for_mspi_tuning()
/hal_espressif-latest/components/hal/esp32c2/include/hal/
Dadc_ll.h99 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_SAMPLE_CYCLE_ADDR, sample_cycle); in adc_ll_set_sample_cycle()
361 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 1); in adc_ll_calibration_init()
378 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 1); in adc_ll_calibration_prepare()
380 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0); in adc_ll_calibration_prepare()
392 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0); in adc_ll_calibration_finish()
408 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb); in adc_ll_set_calibration_param()
409 REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb); in adc_ll_set_calibration_param()

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