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Searched refs:REGDMA_LINK_WRITE_INIT (Results 1 – 5 of 5) sorted by relevance

/hal_espressif-latest/components/esp_hw_support/
Dsleep_modem.c193 …[2] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x00), MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON… in sleep_modem_wifi_modem_state_init()
194 …[3] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x01), MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON… in sleep_modem_wifi_modem_state_init()
197 …[4] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x02), I2C_ANA_MST_ANA_CONF0_REG, 0x8, … in sleep_modem_wifi_modem_state_init()
198 …[5] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x03), PMU_RF_PWR_REG, 0xf0000000,… in sleep_modem_wifi_modem_state_init()
199 …[6] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x04), SARADC_TSENS_REG, SARADC_TSEN… in sleep_modem_wifi_modem_state_init()
200 …[7] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x05), I2C_ANA_MST_I2C_BURST_CONF_REG, 0, … in sleep_modem_wifi_modem_state_init()
202 …[9] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x07), FECOEX_SET_FREQ_SET_CHAN_REG, FECOEX_SET_… in sleep_modem_wifi_modem_state_init()
203 …[10] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x08), FECOEX_SET_FREQ_SET_CHAN_REG, 0, … in sleep_modem_wifi_modem_state_init()
205 …[12] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0a), MODEM_SYSCON_WIFI_BB_CFG_REG, BIT(1), … in sleep_modem_wifi_modem_state_init()
206 …[13] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0b), FECOEX_AGC_CONF_REG, 0, … in sleep_modem_wifi_modem_state_init()
[all …]
Dsleep_system_peripheral.c78 …[0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TEEAPM_LINK(2), TEE_M4_MODE_CTRL_REG, 0x0, 0xfffff… in sleep_sys_periph_tee_apm_retention_init()
94 …[1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_UART_LINK(0x01), UART_REG_UPDATE_REG(0), UART… in sleep_sys_periph_uart0_retention_init()
110 …[0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TIMG_LINK(0x00), TIMG_WDTWPROTECT_REG(0), TIM… in sleep_sys_periph_tg0_retention_init()
112 …[2] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TIMG_LINK(0x02), TIMG_WDTWPROTECT_REG(0), TIM… in sleep_sys_periph_tg0_retention_init()
113 …[3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TIMG_LINK(0x03), TIMG_WDTCONFIG0_REG(0), TIM… in sleep_sys_periph_tg0_retention_init()
114 …[4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TIMG_LINK(0x04), TIMG_T0UPDATE_REG(0), TIM… in sleep_sys_periph_tg0_retention_init()
117 …[7] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TIMG_LINK(0x07), TIMG_T0LOAD_REG(0), 0x1… in sleep_sys_periph_tg0_retention_init()
189 …[0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x00), SYSTIMER_UNIT0_OP_REG, … in sleep_sys_periph_systimer_retention_init()
192 …[3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x03), SYSTIMER_UNIT0_LOAD_REG… in sleep_sys_periph_systimer_retention_init()
194 …[4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x04), SYSTIMER_UNIT1_OP_REG, … in sleep_sys_periph_systimer_retention_init()
[all …]
Dsleep_clock.c43 …[2] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(2), PCR_BUS_CLK_UPDATE_REG, PC… in sleep_clock_system_retention_init()
70 …{ .config = REGDMA_LINK_WRITE_INIT (REGDMA_MODEMSYSCON_LINK(1), MODEM_SYSCON_CLK_CONF1_FORCE_O… in sleep_clock_modem_retention_init()
78 …[0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_MODEMSYSCON_LINK(0xf0), MODEM_SYSCON_CLK_CONF… in sleep_clock_modem_retention_init()
Dsleep_retention.c506 …[0] = { .config = REGDMA_LINK_WRITE_INIT(0xfffe, PMU_DATE_REG, ~value, mask, skip_b, skip_r), .own… in sleep_retention_entries_create_impl()
/hal_espressif-latest/components/esp_hw_support/include/esp_private/
Desp_regdma.h249 #define REGDMA_LINK_WRITE_INIT(_id, _backup, _val, _mask, _skip_b, _skip_r) \ macro