Searched refs:INTENABLE (Results 1 – 10 of 10) sorted by relevance
| /hal_espressif-latest/components/xtensa/ |
| D | xtensa_intr_asm.S | 164 xsr a3, INTENABLE /* Disables all interrupts */
171 wsr a5, INTENABLE /* Reenable interrupts */
175 xsr a3, INTENABLE /* Disables all interrupts */
178 wsr a2, INTENABLE /* Re-enable ints */
213 xsr a3, INTENABLE /* Disables all interrupts */
221 wsr a5, INTENABLE /* Reenable interrupts */
225 xsr a4, INTENABLE /* Disables all interrupts */
229 wsr a3, INTENABLE /* Re-enable ints */
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| /hal_espressif-latest/components/bt/controller/esp32/ |
| D | hli_vectors.S | 60 rsr a0, INTENABLE
64 xsr a0, INTENABLE /* disable all interrupts */
70 wsr a0, INTENABLE /* Enable Timer 2 */
101 xsr a0, INTENABLE /* disable all interrupts */
104 wsr a0, INTENABLE
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| /hal_espressif-latest/components/esp_system/port/soc/esp32s2/ |
| D | highint_hdl.S | 69 rsr a0, INTENABLE
72 wsr a0, INTENABLE
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| /hal_espressif-latest/components/esp_system/port/soc/esp32s3/ |
| D | highint_hdl.S | 77 rsr a0, INTENABLE
80 wsr a0, INTENABLE
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| /hal_espressif-latest/components/xtensa/esp32s2/include/xtensa/config/ |
| D | specreg.h | 72 #define INTENABLE 228 macro
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| /hal_espressif-latest/components/xtensa/esp32/include/xtensa/config/ |
| D | specreg.h | 85 #define INTENABLE 228 macro
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| /hal_espressif-latest/components/xtensa/esp32s3/include/xtensa/config/ |
| D | specreg.h | 85 #define INTENABLE 228 macro
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| /hal_espressif-latest/components/xtensa/include/xtensa/ |
| D | specreg.h | 95 #define INTENABLE 228 macro
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| /hal_espressif-latest/components/esp_system/port/soc/esp32/ |
| D | highint_hdl.S | 183 rsr a0, INTENABLE
250 rsr a0, INTENABLE
253 wsr a0, INTENABLE
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| /hal_espressif-latest/components/xtensa/include/ |
| D | xt_utils.h | 102 RSR(INTENABLE, intr_mask); in xt_utils_intr_get_enabled_mask()
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