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Searched refs:ENTRY (Results 1 – 25 of 47) sorted by relevance

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/hal_espressif-latest/components/esp_hw_support/
Dsleep_system_peripheral.c42 …DR_REG_INTERRUPT_MATRIX_BASE, N_REGS_INTR_MATRIX(), 0, 0), .owner = ENTRY(0) | ENTRY(2) } /* intr… in sleep_sys_periph_intr_matrix_retention_init()
56 …EM_BASE, DR_REG_HP_SYSTEM_BASE, N_REGS_HP_SYSTEM(), 0, 0), .owner = ENTRY(0) | ENTRY(2) } /* hp s… in sleep_sys_periph_hp_system_retention_init()
71 …_REG_HP_APM_BASE, DR_REG_HP_APM_BASE, N_REGS_APM(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* apm … in sleep_sys_periph_tee_apm_retention_init()
72 …_REG_TEE_BASE, DR_REG_TEE_BASE, N_REGS_TEE(), 0, 0), .owner = ENTRY(0) | ENTRY(2) } /* tee … in sleep_sys_periph_tee_apm_retention_init()
78 …WRITE_INIT(REGDMA_TEEAPM_LINK(2), TEE_M4_MODE_CTRL_REG, 0x0, 0xffffffff, 1, 0), .owner = ENTRY(2) } in sleep_sys_periph_tee_apm_retention_init()
92 …RAW_REG(0), UART_INT_RAW_REG(0), N_REGS_UART(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* uart… in sleep_sys_periph_uart0_retention_init()
94 …UART_REG_UPDATE_REG(0), UART_REG_UPDATE, UART_REG_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, in sleep_sys_periph_uart0_retention_init()
95 … UART_REG_UPDATE_REG(0), 0x0, UART_REG_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) } in sleep_sys_periph_uart0_retention_init()
110 …TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, /* TG0 … in sleep_sys_periph_tg0_retention_init()
111 …, REG_TIMG_BASE(0), N_REGS_TG(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, in sleep_sys_periph_tg0_retention_init()
[all …]
Dsleep_clock.c40 … DR_REG_PCR_BASE, N_REGS_PCR(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, in sleep_clock_system_retention_init()
41 …ASS_REG, PCR_RESET_EVENT_BYPASS_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, in sleep_clock_system_retention_init()
43 …REG, PCR_BUS_CLOCK_UPDATE, PCR_BUS_CLOCK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, in sleep_clock_system_retention_init()
44 …REG, 0x0, PCR_BUS_CLOCK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, in sleep_clock_system_retention_init()
68 …F_REG, MODEM_SYSCON_TEST_CONF_REG, N_REGS_SYSCON(), 0, 0), .owner = ENTRY(0) | ENTRY(1) }, /* MODE… in sleep_clock_modem_retention_init()
70 …EM_WIFI_RETENTION_CLOCK, MODEM_WIFI_RETENTION_CLOCK_MASK, 0, 0), .owner = ENTRY(0) }, /* WiFi (MAC… in sleep_clock_modem_retention_init()
73 …ONF_REG, MODEM_LPCON_TEST_CONF_REG, N_REGS_LPCON(), 0, 0), .owner = ENTRY(0) | ENTRY(1) } /* MODEM… in sleep_clock_modem_retention_init()
78 …CONF1_FORCE_ON_REG, 0x0, MODEM_WIFI_RETENTION_CLOCK_MASK, 0, 0), .owner = ENTRY(0) } /* WiFi (MAC… in sleep_clock_modem_retention_init()
/hal_espressif-latest/components/riscv/include/riscv/
Dcsr.h71 #define PMA_ENTRY_SET_TOR(ENTRY, ADDR, CFG) \ argument
73 RV_WRITE_CSR((CSR_PMAADDR0) + (ENTRY), (ADDR) >> (PMA_SHIFT)); \
74 RV_WRITE_CSR((CSR_PMACFG0) + (ENTRY), CFG); \
77 #define PMA_ENTRY_SET_NAPOT(ENTRY, ADDR, SIZE, CFG) \ argument
81 RV_WRITE_CSR((CSR_PMAADDR0) + (ENTRY), ((ADDR) | ((SIZE >> 1) - 1)) >> 2); \
82 RV_WRITE_CSR((CSR_PMACFG0) + (ENTRY), CFG); \
124 #define PMP_ENTRY_SET(ENTRY, ADDR, CFG) do { \ argument
125 RV_WRITE_CSR((CSR_PMPADDR0) + (ENTRY), (ADDR) >> (PMP_SHIFT)); \
126 RV_SET_CSR((CSR_PMPCFG0) + (ENTRY)/4, ((CFG)&0xFF) << (ENTRY%4)*8); \
130 #define PMP_ENTRY_CFG_SET(ENTRY, CFG) do {\ argument
[all …]
/hal_espressif-latest/components/esp_hw_support/port/esp32c6/private_include/
Dsleep_gdma_retention_context.inc26 .owner = ENTRY(0) | ENTRY(2) },
44 .owner = ENTRY(0) | ENTRY(2) },
65 .owner = ENTRY(0) | ENTRY(2) },
71 .owner = ENTRY(0) | ENTRY(2) },
/hal_espressif-latest/components/esp_hw_support/port/esp32h2/private_include/
Dsleep_gdma_retention_context.inc26 .owner = ENTRY(0) | ENTRY(2) },
44 .owner = ENTRY(0) | ENTRY(2) },
65 .owner = ENTRY(0) | ENTRY(2) },
71 .owner = ENTRY(0) | ENTRY(2) },
/hal_espressif-latest/components/esp_phy/src/
Dbtbb_init.c26 #define BTBB_LINK_OWNER ENTRY(3)
28 #define BTBB_LINK_OWNER ENTRY(0) | ENTRY(2)
/hal_espressif-latest/tools/esptool_py/flasher_stub/ld/
Dstub_32s2.ld6 ENTRY(stub_main)
Dstub_32s3.ld6 ENTRY(stub_main)
Dstub_32s3_beta_2.ld6 ENTRY(stub_main)
Dstub_32c2.ld6 ENTRY(stub_main)
Dstub_32c3.ld6 ENTRY(stub_main)
Dstub_32c5_beta_3.ld6 ENTRY(stub_main)
Dstub_32c6.ld6 ENTRY(stub_main)
Dstub_32c6_beta.ld6 ENTRY(stub_main)
Dstub_32h2.ld6 ENTRY(stub_main)
Dstub_32h2_beta_1.ld6 ENTRY(stub_main)
Dstub_32h2_beta_2.ld6 ENTRY(stub_main)
Dstub_32p4.ld6 ENTRY(stub_main)
/hal_espressif-latest/tools/esptool_py/test/images/ram_helloworld/source/ld/
Dapp_32.ld6 ENTRY(ram_main)
Dapp_32c2.ld6 ENTRY(ram_main)
Dapp_32c3.ld6 ENTRY(ram_main)
Dapp_32c5.ld6 ENTRY(ram_main)
Dapp_32c6.ld6 ENTRY(ram_main)
Dapp_32c61.ld6 ENTRY(ram_main)
Dapp_32h2.ld6 ENTRY(ram_main)

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