Searched refs:EFUSE_WR_TIM_CONF0_REG (Results 1 – 7 of 7) sorted by relevance
| /hal_espressif-latest/components/hal/esp32s2/ |
| D | efuse_hal.c | 77 REG_SET_FIELD(EFUSE_WR_TIM_CONF0_REG, EFUSE_TPGM, tpgm); in efuse_hal_set_timing()
78 REG_SET_FIELD(EFUSE_WR_TIM_CONF0_REG, EFUSE_THP_A, thp_a); in efuse_hal_set_timing()
79 REG_SET_FIELD(EFUSE_WR_TIM_CONF0_REG, EFUSE_TPGM_INACTIVE, tpgm_inact); in efuse_hal_set_timing()
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| /hal_espressif-latest/tools/esptool_py/espefuse/efuse/esp32s2/ |
| D | fields.py | 248 self.REGS.EFUSE_WR_TIM_CONF0_REG, self.REGS.EFUSE_TPGM_M, EFUSE_TPGM
251 self.REGS.EFUSE_WR_TIM_CONF0_REG, self.REGS.EFUSE_THP_A_M, EFUSE_THP_A
254 self.REGS.EFUSE_WR_TIM_CONF0_REG,
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| D | mem_definition.py | 75 EFUSE_WR_TIM_CONF0_REG = DR_REG_EFUSE_BASE + 0x1F0 variable in EfuseDefineRegisters
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| /hal_espressif-latest/tools/esptool_py/espefuse/efuse/esp32c2/ |
| D | mem_definition.py | 50 EFUSE_WR_TIM_CONF0_REG = DR_REG_EFUSE_BASE + 0x110 variable in EfuseDefineRegisters
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| D | fields.py | 248 self.REGS.EFUSE_WR_TIM_CONF0_REG,
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| /hal_espressif-latest/components/soc/esp32c2/include/soc/ |
| D | efuse_reg.h | 1143 #define EFUSE_WR_TIM_CONF0_REG (DR_REG_EFUSE_BASE + 0x110) macro
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| /hal_espressif-latest/components/soc/esp32s2/include/soc/ |
| D | efuse_reg.h | 2681 #define EFUSE_WR_TIM_CONF0_REG (DR_REG_EFUSE_BASE + 0x1f0) macro
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