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Searched refs:DR_REG_SHA_BASE (Results 1 – 14 of 14) sorted by relevance

/hal_espressif-latest/components/soc/esp32/include/soc/
Dhwcrypto_reg.h44 #define SHA_TEXT_BASE ((DR_REG_SHA_BASE) + 0x00)
46 #define SHA_1_START_REG ((DR_REG_SHA_BASE) + 0x80)
47 #define SHA_1_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x84)
48 #define SHA_1_LOAD_REG ((DR_REG_SHA_BASE) + 0x88)
49 #define SHA_1_BUSY_REG ((DR_REG_SHA_BASE) + 0x8c)
51 #define SHA_256_START_REG ((DR_REG_SHA_BASE) + 0x90)
52 #define SHA_256_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x94)
53 #define SHA_256_LOAD_REG ((DR_REG_SHA_BASE) + 0x98)
54 #define SHA_256_BUSY_REG ((DR_REG_SHA_BASE) + 0x9c)
56 #define SHA_384_START_REG ((DR_REG_SHA_BASE) + 0xa0)
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Dreg_base.h9 #define DR_REG_SHA_BASE 0x3ff03000 macro
/hal_espressif-latest/components/soc/esp32c2/include/soc/
Dhwcrypto_reg.h16 #define SHA_MODE_REG ((DR_REG_SHA_BASE) + 0x00)
17 #define SHA_BLOCK_NUM_REG ((DR_REG_SHA_BASE) + 0x0C)
18 #define SHA_START_REG ((DR_REG_SHA_BASE) + 0x10)
19 #define SHA_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x14)
20 #define SHA_BUSY_REG ((DR_REG_SHA_BASE) + 0x18)
21 #define SHA_DMA_START_REG ((DR_REG_SHA_BASE) + 0x1C)
22 #define SHA_DMA_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x20)
23 #define SHA_CLEAR_IRQ_REG ((DR_REG_SHA_BASE) + 0x24)
24 #define SHA_INT_ENA_REG ((DR_REG_SHA_BASE) + 0x28)
25 #define SHA_DATE_REG ((DR_REG_SHA_BASE) + 0x2C)
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Dreg_base.h11 #define DR_REG_SHA_BASE 0x6003b000 macro
/hal_espressif-latest/components/soc/esp32c6/include/soc/
Dsha_reg.h17 #define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0)
29 #define SHA_T_STRING_REG (DR_REG_SHA_BASE + 0x4)
41 #define SHA_T_LENGTH_REG (DR_REG_SHA_BASE + 0x8)
53 #define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc)
65 #define SHA_START_REG (DR_REG_SHA_BASE + 0x10)
77 #define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14)
89 #define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18)
101 #define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c)
113 #define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20)
125 #define SHA_CLEAR_IRQ_REG (DR_REG_SHA_BASE + 0x24)
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Dreg_base.h41 #define DR_REG_SHA_BASE 0x60089000 macro
/hal_espressif-latest/components/soc/esp32h2/include/soc/
Dsha_reg.h17 #define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0)
29 #define SHA_T_STRING_REG (DR_REG_SHA_BASE + 0x4)
41 #define SHA_T_LENGTH_REG (DR_REG_SHA_BASE + 0x8)
53 #define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc)
65 #define SHA_START_REG (DR_REG_SHA_BASE + 0x10)
77 #define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14)
89 #define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18)
101 #define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c)
113 #define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20)
125 #define SHA_CLEAR_IRQ_REG (DR_REG_SHA_BASE + 0x24)
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Dreg_base.h32 #define DR_REG_SHA_BASE 0x60089000 macro
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Dhwcrypto_reg.h40 #define SHA_MODE_REG ((DR_REG_SHA_BASE) + 0x00)
41 #define SHA_T_STRING_REG ((DR_REG_SHA_BASE) + 0x04)
42 #define SHA_T_LENGTH_REG ((DR_REG_SHA_BASE) + 0x08)
43 #define SHA_BLOCK_NUM_REG ((DR_REG_SHA_BASE) + 0x0C)
44 #define SHA_START_REG ((DR_REG_SHA_BASE) + 0x10)
45 #define SHA_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x14)
46 #define SHA_BUSY_REG ((DR_REG_SHA_BASE) + 0x18)
47 #define SHA_DMA_START_REG ((DR_REG_SHA_BASE) + 0x1C)
48 #define SHA_DMA_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x20)
49 #define SHA_CLEAR_IRQ_REG ((DR_REG_SHA_BASE) + 0x24)
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Dreg_base.h52 #define DR_REG_SHA_BASE 0x6003B000 macro
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Dhwcrypto_reg.h46 #define SHA_MODE_REG ((DR_REG_SHA_BASE) + 0x00)
47 #define SHA_BLOCK_NUM_REG ((DR_REG_SHA_BASE) + 0x0C)
48 #define SHA_START_REG ((DR_REG_SHA_BASE) + 0x10)
49 #define SHA_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x14)
50 #define SHA_BUSY_REG ((DR_REG_SHA_BASE) + 0x18)
51 #define SHA_DMA_START_REG ((DR_REG_SHA_BASE) + 0x1C)
52 #define SHA_DMA_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x20)
53 #define SHA_CLEAR_IRQ_REG ((DR_REG_SHA_BASE) + 0x24)
54 #define SHA_INT_ENA_REG ((DR_REG_SHA_BASE) + 0x28)
55 #define SHA_DATE_REG ((DR_REG_SHA_BASE) + 0x2C)
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Dreg_base.h12 #define DR_REG_SHA_BASE 0x6003b000 macro
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Dhwcrypto_reg.h50 #define SHA_MODE_REG ((DR_REG_SHA_BASE) + 0x00)
51 #define SHA_T_STRING_REG ((DR_REG_SHA_BASE) + 0x04)
52 #define SHA_T_LENGTH_REG ((DR_REG_SHA_BASE) + 0x08)
53 #define SHA_BLOCK_NUM_REG ((DR_REG_SHA_BASE) + 0x0C)
54 #define SHA_START_REG ((DR_REG_SHA_BASE) + 0x10)
55 #define SHA_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x14)
56 #define SHA_BUSY_REG ((DR_REG_SHA_BASE) + 0x18)
57 #define SHA_DMA_START_REG ((DR_REG_SHA_BASE) + 0x1C)
58 #define SHA_DMA_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x20)
59 #define SHA_CLEAR_IRQ_REG ((DR_REG_SHA_BASE) + 0x24)
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Dreg_base.h15 #define DR_REG_SHA_BASE 0x6003b000 macro