Searched refs:DR_REG_PCR_BASE (Results 1 – 6 of 6) sorted by relevance
17 #define PCR_UART0_CONF_REG (DR_REG_PCR_BASE + 0x0)36 #define PCR_UART0_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x4)77 #define PCR_UART0_PD_CTRL_REG (DR_REG_PCR_BASE + 0x8)96 #define PCR_UART1_CONF_REG (DR_REG_PCR_BASE + 0xc)115 #define PCR_UART1_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x10)156 #define PCR_UART1_PD_CTRL_REG (DR_REG_PCR_BASE + 0x14)175 #define PCR_MSPI_CONF_REG (DR_REG_PCR_BASE + 0x18)201 #define PCR_MSPI_CLK_CONF_REG (DR_REG_PCR_BASE + 0x1c)224 #define PCR_I2C_CONF_REG (DR_REG_PCR_BASE + 0x20)243 #define PCR_I2C_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x24)[all …]
52 #define DR_REG_PCR_BASE 0x60096000 macro
17 #define PCR_UART0_CONF_REG (DR_REG_PCR_BASE + 0x0)43 #define PCR_UART0_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x4)84 #define PCR_UART0_PD_CTRL_REG (DR_REG_PCR_BASE + 0x8)103 #define PCR_UART1_CONF_REG (DR_REG_PCR_BASE + 0xc)129 #define PCR_UART1_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x10)170 #define PCR_UART1_PD_CTRL_REG (DR_REG_PCR_BASE + 0x14)189 #define PCR_MSPI_CONF_REG (DR_REG_PCR_BASE + 0x18)229 #define PCR_MSPI_CLK_CONF_REG (DR_REG_PCR_BASE + 0x1c)243 #define PCR_I2C0_CONF_REG (DR_REG_PCR_BASE + 0x20)269 #define PCR_I2C0_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x24)[all …]
47 #define DR_REG_PCR_BASE 0x60096000 macro
35 #define N_REGS_PCR() (((PCR_SRAM_POWER_CONF_REG - DR_REG_PCR_BASE) / 4) + 1) in sleep_clock_system_retention_init()37 #define N_REGS_PCR() (((PCR_PWDET_SAR_CLK_CONF_REG - DR_REG_PCR_BASE) / 4) + 1) in sleep_clock_system_retention_init()40 …ig = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(0), DR_REG_PCR_BASE, DR_REG_PCR_BASE… in sleep_clock_system_retention_init()
182 #define DR_REG_PCR_BASE 0x60096000 macro193 #define DR_REG_PCR_BASE 0x60096000 macro460 #define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x10c)468 #define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x110)476 #define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x10c)
