Searched refs:DR_REG_GDMA_BASE (Results 1 – 10 of 10) sorted by relevance
14 #define DMA_INT_RAW_CH0_REG (DR_REG_GDMA_BASE + 0x000)107 #define DMA_INT_ST_CH0_REG (DR_REG_GDMA_BASE + 0x004)187 #define DMA_INT_ENA_CH0_REG (DR_REG_GDMA_BASE + 0x008)267 #define DMA_INT_CLR_CH0_REG (DR_REG_GDMA_BASE + 0x00C)347 #define DMA_INT_RAW_CH1_REG (DR_REG_GDMA_BASE + 0x010)440 #define DMA_INT_ST_CH1_REG (DR_REG_GDMA_BASE + 0x014)520 #define DMA_INT_ENA_CH1_REG (DR_REG_GDMA_BASE + 0x018)600 #define DMA_INT_CLR_CH1_REG (DR_REG_GDMA_BASE + 0x01C)680 #define DMA_INT_RAW_CH2_REG (DR_REG_GDMA_BASE + 0x020)773 #define DMA_INT_ST_CH2_REG (DR_REG_GDMA_BASE + 0x024)[all …]
16 #define DR_REG_GDMA_BASE 0x6003f000 macro
15 #define GDMA_IN_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0x0)50 #define GDMA_IN_CONF1_CH0_REG (DR_REG_GDMA_BASE + 0x4)72 #define GDMA_IN_INT_RAW_CH0_REG (DR_REG_GDMA_BASE + 0x8)149 #define GDMA_IN_INT_ST_CH0_REG (DR_REG_GDMA_BASE + 0xC)211 #define GDMA_IN_INT_ENA_CH0_REG (DR_REG_GDMA_BASE + 0x10)273 #define GDMA_IN_INT_CLR_CH0_REG (DR_REG_GDMA_BASE + 0x14)335 #define GDMA_INFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0x18)421 #define GDMA_IN_POP_CH0_REG (DR_REG_GDMA_BASE + 0x1C)435 #define GDMA_IN_LINK_CH0_REG (DR_REG_GDMA_BASE + 0x20)476 #define GDMA_IN_STATE_CH0_REG (DR_REG_GDMA_BASE + 0x24)[all …]
56 #define DR_REG_GDMA_BASE 0x6003F000 macro
17 #define GDMA_IN_INT_RAW_CH0_REG (DR_REG_GDMA_BASE + 0x0)82 #define GDMA_IN_INT_ST_CH0_REG (DR_REG_GDMA_BASE + 0x4)136 #define GDMA_IN_INT_ENA_CH0_REG (DR_REG_GDMA_BASE + 0x8)190 #define GDMA_IN_INT_CLR_CH0_REG (DR_REG_GDMA_BASE + 0xc)244 #define GDMA_IN_INT_RAW_CH1_REG (DR_REG_GDMA_BASE + 0x10)309 #define GDMA_IN_INT_ST_CH1_REG (DR_REG_GDMA_BASE + 0x14)363 #define GDMA_IN_INT_ENA_CH1_REG (DR_REG_GDMA_BASE + 0x18)417 #define GDMA_IN_INT_CLR_CH1_REG (DR_REG_GDMA_BASE + 0x1c)471 #define GDMA_IN_INT_RAW_CH2_REG (DR_REG_GDMA_BASE + 0x20)536 #define GDMA_IN_INT_ST_CH2_REG (DR_REG_GDMA_BASE + 0x24)[all …]
38 #define DR_REG_GDMA_BASE 0x60080000 macro
29 #define DR_REG_GDMA_BASE 0x60080000 macro
17 #define GDMA_INT_RAW_CH0_REG (DR_REG_GDMA_BASE + 0x0)132 #define GDMA_INT_ST_CH0_REG (DR_REG_GDMA_BASE + 0x4)228 #define GDMA_INT_ENA_CH0_REG (DR_REG_GDMA_BASE + 0x8)324 #define GDMA_INT_CLR_CH0_REG (DR_REG_GDMA_BASE + 0xc)420 #define GDMA_AHB_TEST_REG (DR_REG_GDMA_BASE + 0x40)439 #define GDMA_MISC_CONF_REG (DR_REG_GDMA_BASE + 0x44)465 #define GDMA_DATE_REG (DR_REG_GDMA_BASE + 0x48)477 #define GDMA_IN_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0x70)519 #define GDMA_IN_CONF1_CH0_REG (DR_REG_GDMA_BASE + 0x74)531 #define GDMA_INFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0x78)[all …]
13 #define DR_REG_GDMA_BASE 0x6003f000 macro
