Home
last modified time | relevance | path

Searched refs:DR_REG_AES_XTS_BASE (Results 1 – 4 of 4) sorted by relevance

/hal_espressif-latest/components/soc/esp32c2/include/soc/
Dhwcrypto_reg.h31 #define AES_XTS_PLAIN_BASE ((DR_REG_AES_XTS_BASE) + 0x00)
32 #define AES_XTS_SIZE_REG ((DR_REG_AES_XTS_BASE) + 0x40)
33 #define AES_XTS_DESTINATION_REG ((DR_REG_AES_XTS_BASE) + 0x44)
34 #define AES_XTS_PHYSICAL_ADDR_REG ((DR_REG_AES_XTS_BASE) + 0x48)
36 #define AES_XTS_TRIGGER_REG ((DR_REG_AES_XTS_BASE) + 0x4C)
37 #define AES_XTS_RELEASE_REG ((DR_REG_AES_XTS_BASE) + 0x50)
38 #define AES_XTS_DESTROY_REG ((DR_REG_AES_XTS_BASE) + 0x54)
39 #define AES_XTS_STATE_REG ((DR_REG_AES_XTS_BASE) + 0x58)
Dreg_base.h44 #define DR_REG_AES_XTS_BASE 0x600CC000 macro
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Dhwcrypto_reg.h141 #define AES_XTS_PLAIN_BASE ((DR_REG_AES_XTS_BASE) + 0x00)
142 #define AES_XTS_SIZE_REG ((DR_REG_AES_XTS_BASE) + 0x40)
143 #define AES_XTS_DESTINATION_REG ((DR_REG_AES_XTS_BASE) + 0x44)
144 #define AES_XTS_PHYSICAL_ADDR_REG ((DR_REG_AES_XTS_BASE) + 0x48)
146 #define AES_XTS_TRIGGER_REG ((DR_REG_AES_XTS_BASE) + 0x4C)
147 #define AES_XTS_RELEASE_REG ((DR_REG_AES_XTS_BASE) + 0x50)
148 #define AES_XTS_DESTROY_REG ((DR_REG_AES_XTS_BASE) + 0x54)
149 #define AES_XTS_STATE_REG ((DR_REG_AES_XTS_BASE) + 0x58)
150 #define AES_XTS_DATE_REG ((DR_REG_AES_XTS_BASE) + 0x5C)
Dreg_base.h47 #define DR_REG_AES_XTS_BASE 0x600CC000 macro