Searched refs:CLK_LL_PLL_480M_FREQ_MHZ (Results 1 – 12 of 12) sorted by relevance
28 static uint32_t s_cur_pll_freq = CLK_LL_PLL_480M_FREQ_MHZ;317 source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ; in rtc_clk_cpu_freq_mhz_to_config()322 source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ; in rtc_clk_cpu_freq_mhz_to_config()327 source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ; in rtc_clk_cpu_freq_mhz_to_config()382 div = (source_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ) ? 6 : 4; in rtc_clk_cpu_freq_get_config()384 div = (source_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ) ? 3 : 2; in rtc_clk_cpu_freq_get_config()385 … } else if (freq_mhz == CLK_LL_PLL_240M_FREQ_MHZ && source_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ) { in rtc_clk_cpu_freq_get_config()
253 source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ; in rtc_clk_cpu_freq_mhz_to_config()258 source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ; in rtc_clk_cpu_freq_mhz_to_config()263 source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ; in rtc_clk_cpu_freq_mhz_to_config()319 div = (source_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ) ? 6 : 4; in rtc_clk_cpu_freq_get_config()321 div = (source_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ) ? 3 : 2; in rtc_clk_cpu_freq_get_config()322 … } else if (freq_mhz == CLK_LL_PLL_240M_FREQ_MHZ && source_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ) { in rtc_clk_cpu_freq_get_config()
199 source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ; in rtc_clk_cpu_freq_mhz_to_config()204 source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ; in rtc_clk_cpu_freq_mhz_to_config()260 div = (source_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ) ? 6 : 4; in rtc_clk_cpu_freq_get_config()262 div = (source_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ) ? 3 : 2; in rtc_clk_cpu_freq_get_config()
211 clk_ll_cpu_set_hs_divider(CLK_LL_PLL_480M_FREQ_MHZ / cpu_freq_mhz); in rtc_clk_cpu_freq_to_pll_mhz()237 source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ; in rtc_clk_cpu_freq_mhz_to_config()242 source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ; in rtc_clk_cpu_freq_mhz_to_config()247 source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ; in rtc_clk_cpu_freq_mhz_to_config()
174 source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ; in rtc_clk_cpu_freq_mhz_to_config()179 source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ; in rtc_clk_cpu_freq_mhz_to_config()231 source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ; // PLL clock on ESP32-C2 was fixed to 480MHz in rtc_clk_cpu_freq_get_config()
34 #define CLK_LL_PLL_480M_FREQ_MHZ (480) macro274 return CLK_LL_PLL_480M_FREQ_MHZ; in clk_ll_bbpll_get_freq_mhz()291 case CLK_LL_PLL_480M_FREQ_MHZ: // PLL_480M in clk_ll_bbpll_set_freq_mhz()315 if (pll_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ) { in clk_ll_bbpll_set_config()
32 #define CLK_LL_PLL_480M_FREQ_MHZ (480) macro272 return CLK_LL_PLL_480M_FREQ_MHZ; in clk_ll_bbpll_get_freq_mhz()289 case CLK_LL_PLL_480M_FREQ_MHZ: // PLL_480M in clk_ll_bbpll_set_freq_mhz()313 if (pll_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ) { in clk_ll_bbpll_set_config()
34 #define CLK_LL_PLL_480M_FREQ_MHZ (480) macro358 return CLK_LL_PLL_480M_FREQ_MHZ; in clk_ll_bbpll_get_freq_mhz()375 case CLK_LL_PLL_480M_FREQ_MHZ: // PLL_480M in clk_ll_bbpll_set_freq_mhz()399 if (pll_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ) { in clk_ll_bbpll_set_config()
37 #define CLK_LL_PLL_480M_FREQ_MHZ (480) macro279 return CLK_LL_PLL_480M_FREQ_MHZ; in clk_ll_bbpll_get_freq_mhz()291 HAL_ASSERT(pll_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ); in clk_ll_bbpll_set_freq_mhz()302 HAL_ASSERT(pll_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ); in clk_ll_bbpll_set_config()
33 #define CLK_LL_PLL_480M_FREQ_MHZ (480) macro204 return CLK_LL_PLL_480M_FREQ_MHZ; in clk_ll_bbpll_get_freq_mhz()219 HAL_ASSERT(pll_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ); in clk_ll_bbpll_set_freq_mhz()
445 source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ; in rtc_clk_cpu_freq_mhz_to_config()508 source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ; in rtc_clk_cpu_freq_get_config()
35 #define CLK_LL_PLL_480M_FREQ_MHZ (480) macro408 return CLK_LL_PLL_480M_FREQ_MHZ; in clk_ll_bbpll_get_freq_mhz()
