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Searched refs:CLINT_UINT_SIP_REG (Results 1 – 3 of 3) sorted by relevance

/hal_espressif-latest/components/soc/esp32c6/include/soc/
Dclint_reg.h87 #define CLINT_UINT_SIP_REG (DR_REG_CLINT_U_BASE + 0x0) macro
/hal_espressif-latest/components/soc/esp32h2/include/soc/
Dclint_reg.h89 #define CLINT_UINT_SIP_REG (DR_REG_CLINT_U_BASE + 0x0) macro
/hal_espressif-latest/components/esp_hw_support/
Dsleep_cpu.c354 { .start = CLINT_UINT_SIP_REG, .end = CLINT_UINT_UTIMECMP_H_REG + 4 } in cpu_domain_clint_sleep_frame_alloc_and_init()