Searched refs:CACHE_LL_L1_ILG_EVENT_MASK (Results 1 – 6 of 6) sorted by relevance
| /hal_espressif-latest/components/esp_system/port/soc/esp32c2/ |
| D | cache_err_int.c | 67 ESP_DRAM_LOGV(TAG, "illegal error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ILG_EVENT_MASK); in esp_cache_err_int_init()
68 cache_ll_l1_clear_illegal_error_intr(0, CACHE_LL_L1_ILG_EVENT_MASK); in esp_cache_err_int_init()
69 cache_ll_l1_enable_illegal_error_intr(0, CACHE_LL_L1_ILG_EVENT_MASK); in esp_cache_err_int_init()
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| /hal_espressif-latest/components/esp_system/port/soc/esp32c3/ |
| D | cache_err_int.c | 67 ESP_DRAM_LOGV(TAG, "illegal error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ILG_EVENT_MASK); in esp_cache_err_int_init()
68 cache_ll_l1_clear_illegal_error_intr(0, CACHE_LL_L1_ILG_EVENT_MASK); in esp_cache_err_int_init()
69 cache_ll_l1_enable_illegal_error_intr(0, CACHE_LL_L1_ILG_EVENT_MASK); in esp_cache_err_int_init()
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| /hal_espressif-latest/components/esp_system/port/soc/esp32s3/ |
| D | cache_err_int.c | 47 ESP_DRAM_LOGV(TAG, "illegal error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ILG_EVENT_MASK); in esp_cache_err_int_init()
49 cache_ll_l1_clear_illegal_error_intr(0, CACHE_LL_L1_ILG_EVENT_MASK); in esp_cache_err_int_init()
50 cache_ll_l1_enable_illegal_error_intr(0, CACHE_LL_L1_ILG_EVENT_MASK); in esp_cache_err_int_init()
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| /hal_espressif-latest/components/hal/esp32c2/include/hal/ |
| D | cache_ll.h | 33 #define CACHE_LL_L1_ILG_EVENT_MASK (0x23) macro
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| /hal_espressif-latest/components/hal/esp32c3/include/hal/ |
| D | cache_ll.h | 33 #define CACHE_LL_L1_ILG_EVENT_MASK (0x23) macro
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| /hal_espressif-latest/components/hal/esp32s3/include/hal/ |
| D | cache_ll.h | 33 #define CACHE_LL_L1_ILG_EVENT_MASK (0x3f) macro
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