Searched refs:CACHE_BUS_IBUS0 (Results 1 – 15 of 15) sorted by relevance
22 #define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS071 mask |= CACHE_BUS_IBUS0; in cache_ll_l1_get_bus()75 mask |= (vaddr_end >= IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0; in cache_ll_l1_get_bus()80 mask |= (vaddr_end >= IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0; in cache_ll_l1_get_bus()86 mask |= (vaddr_end >= IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0; in cache_ll_l1_get_bus()93 mask |= (vaddr_end >= IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0; in cache_ll_l1_get_bus()116 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_PRO_ICACHE_MASK_IRAM0 : 0; in cache_ll_l1_enable_bus()140 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_PRO_ICACHE_MASK_IRAM0 : 0; in cache_ll_l1_disable_bus()
23 #define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS085 mask |= CACHE_BUS_IBUS0; //Both cores have their own IBUS0 in cache_ll_l1_get_bus()112 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE0_BUS : 0; in cache_ll_l1_enable_bus()114 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE1_BUS : 0; in cache_ll_l1_enable_bus()143 mask |= (!(ibus_mask & EXTMEM_ICACHE_SHUT_CORE0_BUS)) ? CACHE_BUS_IBUS0 : 0; in cache_ll_l1_get_enabled_bus()145 mask |= (!(ibus_mask & EXTMEM_ICACHE_SHUT_CORE1_BUS)) ? CACHE_BUS_IBUS0 : 0; in cache_ll_l1_get_enabled_bus()173 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE0_BUS : 0; in cache_ll_l1_disable_bus()175 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE1_BUS : 0; in cache_ll_l1_disable_bus()
109 mask |= CACHE_BUS_IBUS0; in cache_ll_l1_get_bus()142 bus_mask |= (mask & CACHE_BUS_IBUS0) ? DPORT_PRO_CACHE_MASK_IRAM0 : 0; in cache_ll_l1_enable_bus()151 bus_mask |= (mask & CACHE_BUS_IBUS0) ? DPORT_APP_CACHE_MASK_IRAM0 : 0; in cache_ll_l1_enable_bus()176 mask |= (!(bus_mask & DPORT_PRO_CACHE_MASK_IRAM0)) ? CACHE_BUS_IBUS0 : 0; in cache_ll_l1_get_enabled_bus()184 mask |= (!(bus_mask & DPORT_APP_CACHE_MASK_IRAM0)) ? CACHE_BUS_IBUS0 : 0; in cache_ll_l1_get_enabled_bus()209 bus_mask |= (mask & CACHE_BUS_IBUS0) ? DPORT_PRO_CACHE_MASK_IRAM0 : 0; in cache_ll_l1_disable_bus()218 bus_mask |= (mask & CACHE_BUS_IBUS0) ? DPORT_APP_CACHE_MASK_IRAM0 : 0; in cache_ll_l1_disable_bus()
21 #define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS049 mask |= CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0; in cache_ll_l1_get_bus()73 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0; in cache_ll_l1_enable_bus()95 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0; in cache_ll_l1_disable_bus()
21 #define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS049 mask |= CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0; in cache_ll_l1_get_bus()73 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_L1_CACHE_SHUT_IBUS : 0; in cache_ll_l1_enable_bus()95 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_L1_CACHE_SHUT_IBUS : 0; in cache_ll_l1_disable_bus()
22 #define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS073 mask |= CACHE_BUS_IBUS0; in cache_ll_l1_get_bus()99 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0; in cache_ll_l1_enable_bus()121 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0; in cache_ll_l1_disable_bus()
22 #define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS074 mask |= CACHE_BUS_IBUS0; in cache_ll_l1_get_bus()100 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0; in cache_ll_l1_enable_bus()122 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0; in cache_ll_l1_disable_bus()
21 .bus_id = CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0,
29 CACHE_BUS_IBUS0 = BIT(0), enumerator
22 .bus_id = CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0,
22 .bus_id = CACHE_BUS_IBUS0,