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Searched refs:CACHE_BUS_DBUS1 (Results 1 – 10 of 10) sorted by relevance

/hal_espressif-latest/components/hal/esp32/include/hal/
Dcache_ll.h114 mask |= CACHE_BUS_DBUS1; in cache_ll_l1_get_bus()
147 bus_mask |= (mask & CACHE_BUS_DBUS1) ? DPORT_PRO_CACHE_MASK_DRAM1 : 0; in cache_ll_l1_enable_bus()
156 bus_mask |= (mask & CACHE_BUS_DBUS1) ? DPORT_APP_CACHE_MASK_DRAM1 : 0; in cache_ll_l1_enable_bus()
181 mask |= (!(bus_mask & DPORT_PRO_CACHE_MASK_DRAM1)) ? CACHE_BUS_DBUS1 : 0; in cache_ll_l1_get_enabled_bus()
189 mask |= (!(bus_mask & DPORT_APP_CACHE_MASK_DRAM1)) ? CACHE_BUS_DBUS1 : 0; in cache_ll_l1_get_enabled_bus()
214 bus_mask |= (mask & CACHE_BUS_DBUS1) ? DPORT_PRO_CACHE_MASK_DRAM1 : 0; in cache_ll_l1_disable_bus()
223 bus_mask |= (mask & CACHE_BUS_DBUS1) ? DPORT_APP_CACHE_MASK_DRAM1 : 0; in cache_ll_l1_disable_bus()
/hal_espressif-latest/components/hal/esp32s2/include/hal/
Dcache_ll.h78 mask |= CACHE_BUS_DBUS1; in cache_ll_l1_get_bus()
84 mask |= (vaddr_end >= DRAM1_ADDRESS_LOW) ? CACHE_BUS_DBUS1 : 0; in cache_ll_l1_get_bus()
91 mask |= (vaddr_end >= DRAM1_ADDRESS_LOW) ? CACHE_BUS_DBUS1 : 0; in cache_ll_l1_get_bus()
123 dbus_mask |= (mask & CACHE_BUS_DBUS1) ? EXTMEM_PRO_DCACHE_MASK_DRAM1 : 0; in cache_ll_l1_enable_bus()
147 dbus_mask |= (mask & CACHE_BUS_DBUS1) ? EXTMEM_PRO_DCACHE_MASK_DRAM1 : 0; in cache_ll_l1_disable_bus()
/hal_espressif-latest/components/hal/esp32h2/include/hal/
Dcache_ll.h70 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_enable_bus()
92 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_disable_bus()
/hal_espressif-latest/components/hal/esp32c6/include/hal/
Dcache_ll.h70 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_enable_bus()
92 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_disable_bus()
/hal_espressif-latest/components/hal/esp32c2/include/hal/
Dcache_ll.h96 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_enable_bus()
118 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_disable_bus()
/hal_espressif-latest/components/hal/esp32c3/include/hal/
Dcache_ll.h97 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_enable_bus()
119 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_disable_bus()
/hal_espressif-latest/components/hal/include/hal/
Dcache_types.h33 CACHE_BUS_DBUS1 = BIT(4), enumerator
/hal_espressif-latest/components/esp_mm/port/esp32/
Dext_mem_layout.c38 .bus_id = CACHE_BUS_DBUS1,
/hal_espressif-latest/components/hal/esp32s3/include/hal/
Dcache_ll.h108 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_enable_bus()
169 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_disable_bus()
/hal_espressif-latest/components/esp_mm/port/esp32s2/
Dext_mem_layout.c46 .bus_id = CACHE_BUS_DBUS1,