Searched refs:CACHE_BUS_DBUS0 (Results 1 – 15 of 15) sorted by relevance
24 #define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS087 mask |= CACHE_BUS_DBUS0; //Both cores have their own DBUS0 in cache_ll_l1_get_bus()120 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE0_BUS : 0; in cache_ll_l1_enable_bus()122 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE1_BUS : 0; in cache_ll_l1_enable_bus()150 mask |= (!(dbus_mask & EXTMEM_DCACHE_SHUT_CORE0_BUS)) ? CACHE_BUS_DBUS0 : 0; in cache_ll_l1_get_enabled_bus()152 mask |= (!(dbus_mask & EXTMEM_DCACHE_SHUT_CORE1_BUS)) ? CACHE_BUS_DBUS0 : 0; in cache_ll_l1_get_enabled_bus()181 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE0_BUS : 0; in cache_ll_l1_disable_bus()183 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE1_BUS : 0; in cache_ll_l1_disable_bus()
74 mask |= CACHE_BUS_DBUS0; in cache_ll_l1_get_bus()79 mask |= (vaddr_end >= DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0; in cache_ll_l1_get_bus()85 mask |= (vaddr_end >= DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0; in cache_ll_l1_get_bus()92 mask |= (vaddr_end >= DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0; in cache_ll_l1_get_bus()122 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_PRO_DCACHE_MASK_DRAM0 : 0; in cache_ll_l1_enable_bus()146 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_PRO_DCACHE_MASK_DRAM0 : 0; in cache_ll_l1_disable_bus()
117 mask |= CACHE_BUS_DBUS0; in cache_ll_l1_get_bus()146 bus_mask |= (mask & CACHE_BUS_DBUS0) ? DPORT_PRO_CACHE_MASK_DROM0 : 0; in cache_ll_l1_enable_bus()155 bus_mask |= (mask & CACHE_BUS_DBUS0) ? DPORT_APP_CACHE_MASK_DROM0 : 0; in cache_ll_l1_enable_bus()180 mask |= (!(bus_mask & DPORT_PRO_CACHE_MASK_DROM0)) ? CACHE_BUS_DBUS0 : 0; in cache_ll_l1_get_enabled_bus()188 mask |= (!(bus_mask & DPORT_APP_CACHE_MASK_DROM0)) ? CACHE_BUS_DBUS0 : 0; in cache_ll_l1_get_enabled_bus()213 bus_mask |= (mask & CACHE_BUS_DBUS0) ? DPORT_PRO_CACHE_MASK_DROM0 : 0; in cache_ll_l1_disable_bus()222 bus_mask |= (mask & CACHE_BUS_DBUS0) ? DPORT_APP_CACHE_MASK_DROM0 : 0; in cache_ll_l1_disable_bus()
22 #define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS049 mask |= CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0; in cache_ll_l1_get_bus()77 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0; in cache_ll_l1_enable_bus()99 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0; in cache_ll_l1_disable_bus()
22 #define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS049 mask |= CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0; in cache_ll_l1_get_bus()77 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_L1_CACHE_SHUT_DBUS : 0; in cache_ll_l1_enable_bus()99 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_L1_CACHE_SHUT_DBUS : 0; in cache_ll_l1_disable_bus()
23 #define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS075 mask |= CACHE_BUS_DBUS0; in cache_ll_l1_get_bus()103 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0; in cache_ll_l1_enable_bus()125 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0; in cache_ll_l1_disable_bus()
23 #define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS076 mask |= CACHE_BUS_DBUS0; in cache_ll_l1_get_bus()104 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0; in cache_ll_l1_enable_bus()126 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0; in cache_ll_l1_disable_bus()
21 .bus_id = CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0,
32 CACHE_BUS_DBUS0 = BIT(3), enumerator
22 .bus_id = CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0,
30 .bus_id = CACHE_BUS_DBUS0,
54 .bus_id = CACHE_BUS_DBUS0,
