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/hal_espressif-latest/components/soc/esp32/include/soc/
Dslc_reg.h22 #define SLC_SLC1_TOKEN_SEL (BIT(31))
23 #define SLC_SLC1_TOKEN_SEL_M (BIT(31))
28 #define SLC_SLC1_TOKEN_AUTO_CLR (BIT(30))
29 #define SLC_SLC1_TOKEN_AUTO_CLR_M (BIT(30))
34 #define SLC_SLC1_TXDATA_BURST_EN (BIT(29))
35 #define SLC_SLC1_TXDATA_BURST_EN_M (BIT(29))
40 #define SLC_SLC1_TXDSCR_BURST_EN (BIT(28))
41 #define SLC_SLC1_TXDSCR_BURST_EN_M (BIT(28))
46 #define SLC_SLC1_TXLINK_AUTO_RET (BIT(27))
47 #define SLC_SLC1_TXLINK_AUTO_RET_M (BIT(27))
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Dhost_reg.h22 #define HOST_SLC_FUNC2_INT (BIT(24))
23 #define HOST_SLC_FUNC2_INT_M (BIT(24))
30 #define HOST_SLC_FUNC2_INT_EN (BIT(0))
31 #define HOST_SLC_FUNC2_INT_EN_M (BIT(0))
38 #define HOST_SLC_FUNC1_MDSTAT (BIT(0))
39 #define HOST_SLC_FUNC1_MDSTAT_M (BIT(0))
90 #define HOST_SLC0_RX_PF_VALID (BIT(12))
91 #define HOST_SLC0_RX_PF_VALID_M (BIT(12))
120 #define HOST_GPIO_SDIO_INT_RAW (BIT(25))
121 #define HOST_GPIO_SDIO_INT_RAW_M (BIT(25))
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Drtc_cntl_reg.h26 #define RTC_CNTL_SW_SYS_RST (BIT(31))
27 #define RTC_CNTL_SW_SYS_RST_M (BIT(31))
32 #define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30))
33 #define RTC_CNTL_DG_WRAP_FORCE_NORST_M (BIT(30))
38 #define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29))
39 #define RTC_CNTL_DG_WRAP_FORCE_RST_M (BIT(29))
44 #define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28))
45 #define RTC_CNTL_ANALOG_FORCE_NOISO_M (BIT(28))
50 #define RTC_CNTL_PLL_FORCE_NOISO (BIT(27))
51 #define RTC_CNTL_PLL_FORCE_NOISO_M (BIT(27))
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Drtc_io_reg.h102 #define RTC_GPIO_PIN0_WAKEUP_ENABLE (BIT(10))
103 #define RTC_GPIO_PIN0_WAKEUP_ENABLE_M (BIT(10))
115 #define RTC_GPIO_PIN0_PAD_DRIVER (BIT(2))
116 #define RTC_GPIO_PIN0_PAD_DRIVER_M (BIT(2))
123 #define RTC_GPIO_PIN1_WAKEUP_ENABLE (BIT(10))
124 #define RTC_GPIO_PIN1_WAKEUP_ENABLE_M (BIT(10))
136 #define RTC_GPIO_PIN1_PAD_DRIVER (BIT(2))
137 #define RTC_GPIO_PIN1_PAD_DRIVER_M (BIT(2))
144 #define RTC_GPIO_PIN2_WAKEUP_ENABLE (BIT(10))
145 #define RTC_GPIO_PIN2_WAKEUP_ENABLE_M (BIT(10))
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Drmt_reg.h34 #define RMT_CLK_EN (BIT(31))
35 #define RMT_CLK_EN_M (BIT(31))
40 #define RMT_MEM_PD (BIT(30))
41 #define RMT_MEM_PD_M (BIT(30))
47 #define RMT_CARRIER_OUT_LV_CH0 (BIT(29))
48 #define RMT_CARRIER_OUT_LV_CH0_M (BIT(29))
53 #define RMT_CARRIER_EN_CH0 (BIT(28))
54 #define RMT_CARRIER_EN_CH0_M (BIT(28))
81 #define RMT_IDLE_OUT_EN_CH0 (BIT(19))
82 #define RMT_IDLE_OUT_EN_CH0_M (BIT(19))
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/hal_espressif-latest/components/soc/esp32s3/include/soc/
Dgdma_reg.h19 #define GDMA_MEM_TRANS_EN_CH0 (BIT(4))
20 #define GDMA_MEM_TRANS_EN_CH0_M (BIT(4))
26 #define GDMA_IN_DATA_BURST_EN_CH0 (BIT(3))
27 #define GDMA_IN_DATA_BURST_EN_CH0_M (BIT(3))
33 #define GDMA_INDSCR_BURST_EN_CH0 (BIT(2))
34 #define GDMA_INDSCR_BURST_EN_CH0_M (BIT(2))
39 #define GDMA_IN_LOOP_TEST_CH0 (BIT(1))
40 #define GDMA_IN_LOOP_TEST_CH0_M (BIT(1))
45 #define GDMA_IN_RST_CH0 (BIT(0))
46 #define GDMA_IN_RST_CH0_M (BIT(0))
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Dspi_reg.h28 #define SPI_USR (BIT(24))
29 #define SPI_USR_M (BIT(24))
35 #define SPI_UPDATE (BIT(23))
36 #define SPI_UPDATE_M (BIT(23))
72 #define SPI_WP_POL (BIT(21))
73 #define SPI_WP_POL_M (BIT(21))
79 #define SPI_HOLD_POL (BIT(20))
80 #define SPI_HOLD_POL_M (BIT(20))
86 #define SPI_D_POL (BIT(19))
87 #define SPI_D_POL_M (BIT(19))
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Drtc_cntl_reg.h25 #define RTC_CNTL_SW_SYS_RST (BIT(31))
26 #define RTC_CNTL_SW_SYS_RST_M (BIT(31))
31 #define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30))
32 #define RTC_CNTL_DG_WRAP_FORCE_NORST_M (BIT(30))
37 #define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29))
38 #define RTC_CNTL_DG_WRAP_FORCE_RST_M (BIT(29))
43 #define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28))
44 #define RTC_CNTL_ANALOG_FORCE_NOISO_M (BIT(28))
49 #define RTC_CNTL_PLL_FORCE_NOISO (BIT(27))
50 #define RTC_CNTL_PLL_FORCE_NOISO_M (BIT(27))
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Drtc_io_reg.h106 #define RTC_GPIO_PIN0_WAKEUP_ENABLE (BIT(10))
107 #define RTC_GPIO_PIN0_WAKEUP_ENABLE_M (BIT(10))
120 #define RTC_GPIO_PIN0_PAD_DRIVER (BIT(2))
121 #define RTC_GPIO_PIN0_PAD_DRIVER_M (BIT(2))
128 #define RTC_GPIO_PIN1_WAKEUP_ENABLE (BIT(10))
129 #define RTC_GPIO_PIN1_WAKEUP_ENABLE_M (BIT(10))
142 #define RTC_GPIO_PIN1_PAD_DRIVER (BIT(2))
143 #define RTC_GPIO_PIN1_PAD_DRIVER_M (BIT(2))
150 #define RTC_GPIO_PIN2_WAKEUP_ENABLE (BIT(10))
151 #define RTC_GPIO_PIN2_WAKEUP_ENABLE_M (BIT(10))
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Dsystem_reg.h26 #define SYSTEM_CONTROL_CORE_1_RESETTING (BIT(2))
27 #define SYSTEM_CONTROL_CORE_1_RESETTING_M (BIT(2))
32 #define SYSTEM_CONTROL_CORE_1_CLKGATE_EN (BIT(1))
33 #define SYSTEM_CONTROL_CORE_1_CLKGATE_EN_M (BIT(1))
38 #define SYSTEM_CONTROL_CORE_1_RUNSTALL (BIT(0))
39 #define SYSTEM_CONTROL_CORE_1_RUNSTALL_M (BIT(0))
54 #define SYSTEM_CLK_EN_DEDICATED_GPIO (BIT(7))
55 #define SYSTEM_CLK_EN_DEDICATED_GPIO_M (BIT(7))
60 #define SYSTEM_CLK_EN_ASSIST_DEBUG (BIT(6))
61 #define SYSTEM_CLK_EN_ASSIST_DEBUG_M (BIT(6))
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/hal_espressif-latest/components/soc/esp32c3/include/soc/
Dgdma_reg.h18 #define DMA_OUTFIFO_UDF_CH0_INT_RAW (BIT(12))
19 #define DMA_OUTFIFO_UDF_CH0_INT_RAW_M (BIT(12))
25 #define DMA_OUTFIFO_OVF_CH0_INT_RAW (BIT(11))
26 #define DMA_OUTFIFO_OVF_CH0_INT_RAW_M (BIT(11))
32 #define DMA_INFIFO_UDF_CH0_INT_RAW (BIT(10))
33 #define DMA_INFIFO_UDF_CH0_INT_RAW_M (BIT(10))
39 #define DMA_INFIFO_OVF_CH0_INT_RAW (BIT(9))
40 #define DMA_INFIFO_OVF_CH0_INT_RAW_M (BIT(9))
46 #define DMA_OUT_TOTAL_EOF_CH0_INT_RAW (BIT(8))
47 #define DMA_OUT_TOTAL_EOF_CH0_INT_RAW_M (BIT(8))
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Dsystem_reg.h25 #define SYSTEM_CLK_EN_DEDICATED_GPIO (BIT(7))
26 #define SYSTEM_CLK_EN_DEDICATED_GPIO_M (BIT(7))
31 #define SYSTEM_CLK_EN_ASSIST_DEBUG (BIT(6))
32 #define SYSTEM_CLK_EN_ASSIST_DEBUG_M (BIT(6))
39 #define SYSTEM_RST_EN_DEDICATED_GPIO (BIT(7))
40 #define SYSTEM_RST_EN_DEDICATED_GPIO_M (BIT(7))
45 #define SYSTEM_RST_EN_ASSIST_DEBUG (BIT(6))
46 #define SYSTEM_RST_EN_ASSIST_DEBUG_M (BIT(6))
59 #define SYSTEM_CPU_WAIT_MODE_FORCE_ON (BIT(3))
60 #define SYSTEM_CPU_WAIT_MODE_FORCE_ON_M (BIT(3))
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Drmt_reg.h25 #define RMT_CONF_UPDATE_CH0 (BIT(24))
26 #define RMT_CONF_UPDATE_CH0_M (BIT(24))
31 #define RMT_AFIFO_RST_CH0 (BIT(23))
32 #define RMT_AFIFO_RST_CH0_M (BIT(23))
37 #define RMT_CARRIER_OUT_LV_CH0 (BIT(22))
38 #define RMT_CARRIER_OUT_LV_CH0_M (BIT(22))
43 #define RMT_CARRIER_EN_CH0 (BIT(21))
44 #define RMT_CARRIER_EN_CH0_M (BIT(21))
49 #define RMT_CARRIER_EFF_EN_CH0 (BIT(20))
50 #define RMT_CARRIER_EFF_EN_CH0_M (BIT(20))
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Dspi_reg.h20 #define SPI_USR (BIT(24))
21 #define SPI_USR_M (BIT(24))
27 #define SPI_UPDATE (BIT(23))
28 #define SPI_UPDATE_M (BIT(23))
50 #define SPI_WR_BIT_ORDER (BIT(26))
51 #define SPI_WR_BIT_ORDER_M (BIT(26))
57 #define SPI_RD_BIT_ORDER (BIT(25))
58 #define SPI_RD_BIT_ORDER_M (BIT(25))
64 #define SPI_WP_POL (BIT(21))
65 #define SPI_WP_POL_M (BIT(21))
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Drtc_cntl_reg.h35 #define RTC_CNTL_SW_SYS_RST (BIT(31))
36 #define RTC_CNTL_SW_SYS_RST_M (BIT(31))
41 #define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30))
42 #define RTC_CNTL_DG_WRAP_FORCE_NORST_M (BIT(30))
47 #define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29))
48 #define RTC_CNTL_DG_WRAP_FORCE_RST_M (BIT(29))
53 #define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28))
54 #define RTC_CNTL_ANALOG_FORCE_NOISO_M (BIT(28))
59 #define RTC_CNTL_PLL_FORCE_NOISO (BIT(27))
60 #define RTC_CNTL_PLL_FORCE_NOISO_M (BIT(27))
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Duart_reg.h34 #define UART_WAKEUP_INT_RAW (BIT(19))
35 #define UART_WAKEUP_INT_RAW_M (BIT(19))
41 #define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18))
42 #define UART_AT_CMD_CHAR_DET_INT_RAW_M (BIT(18))
48 #define UART_RS485_CLASH_INT_RAW (BIT(17))
49 #define UART_RS485_CLASH_INT_RAW_M (BIT(17))
55 #define UART_RS485_FRM_ERR_INT_RAW (BIT(16))
56 #define UART_RS485_FRM_ERR_INT_RAW_M (BIT(16))
62 #define UART_RS485_PARITY_ERR_INT_RAW (BIT(15))
63 #define UART_RS485_PARITY_ERR_INT_RAW_M (BIT(15))
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/hal_espressif-latest/components/soc/esp32s2/include/soc/
Dsensitive_reg.h25 #define DPORT_PMS_SDIO_LOCK (BIT(0))
26 #define DPORT_PMS_SDIO_LOCK_M (BIT(0))
33 #define DPORT_PMS_SDIO_DISABLE (BIT(0))
34 #define DPORT_PMS_SDIO_DISABLE_M (BIT(0))
41 #define DPORT_PMS_MAC_DUMP_LOCK (BIT(0))
42 #define DPORT_PMS_MAC_DUMP_LOCK_M (BIT(0))
57 #define DPORT_PMS_PRO_IRAM0_LOCK (BIT(0))
58 #define DPORT_PMS_PRO_IRAM0_LOCK_M (BIT(0))
65 #define DPORT_PMS_PRO_IRAM0_SRAM_3_W (BIT(11))
66 #define DPORT_PMS_PRO_IRAM0_SRAM_3_W_M (BIT(11))
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Drtc_cntl_reg.h32 #define RTC_CNTL_SW_SYS_RST (BIT(31))
33 #define RTC_CNTL_SW_SYS_RST_M (BIT(31))
38 #define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30))
39 #define RTC_CNTL_DG_WRAP_FORCE_NORST_M (BIT(30))
44 #define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29))
45 #define RTC_CNTL_DG_WRAP_FORCE_RST_M (BIT(29))
50 #define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28))
51 #define RTC_CNTL_ANALOG_FORCE_NOISO_M (BIT(28))
56 #define RTC_CNTL_PLL_FORCE_NOISO (BIT(27))
57 #define RTC_CNTL_PLL_FORCE_NOISO_M (BIT(27))
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Drtc_io_reg.h105 #define RTC_GPIO_PIN0_WAKEUP_ENABLE (BIT(10))
106 #define RTC_GPIO_PIN0_WAKEUP_ENABLE_M (BIT(10))
118 #define RTC_GPIO_PIN0_PAD_DRIVER (BIT(2))
119 #define RTC_GPIO_PIN0_PAD_DRIVER_M (BIT(2))
126 #define RTC_GPIO_PIN1_WAKEUP_ENABLE (BIT(10))
127 #define RTC_GPIO_PIN1_WAKEUP_ENABLE_M (BIT(10))
139 #define RTC_GPIO_PIN1_PAD_DRIVER (BIT(2))
140 #define RTC_GPIO_PIN1_PAD_DRIVER_M (BIT(2))
147 #define RTC_GPIO_PIN2_WAKEUP_ENABLE (BIT(10))
148 #define RTC_GPIO_PIN2_WAKEUP_ENABLE_M (BIT(10))
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Duart_reg.h33 #define UART_WAKEUP_INT_RAW (BIT(19))
34 #define UART_WAKEUP_INT_RAW_M (BIT(19))
39 #define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18))
40 #define UART_AT_CMD_CHAR_DET_INT_RAW_M (BIT(18))
45 #define UART_RS485_CLASH_INT_RAW (BIT(17))
46 #define UART_RS485_CLASH_INT_RAW_M (BIT(17))
51 #define UART_RS485_FRM_ERR_INT_RAW (BIT(16))
52 #define UART_RS485_FRM_ERR_INT_RAW_M (BIT(16))
57 #define UART_RS485_PARITY_ERR_INT_RAW (BIT(15))
58 #define UART_RS485_PARITY_ERR_INT_RAW_M (BIT(15))
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Dsystem_reg.h56 #define DPORT_CLK_EN_DEDICATED_GPIO (BIT(7))
57 #define DPORT_CLK_EN_DEDICATED_GPIO_M (BIT(7))
62 #define DPORT_CLK_EN_ASSIST_DEBUG (BIT(6))
63 #define DPORT_CLK_EN_ASSIST_DEBUG_M (BIT(6))
74 #define DPORT_RST_EN_DEDICATED_GPIO (BIT(7))
75 #define DPORT_RST_EN_DEDICATED_GPIO_M (BIT(7))
80 #define DPORT_RST_EN_ASSIST_DEBUG (BIT(6))
81 #define DPORT_RST_EN_ASSIST_DEBUG_M (BIT(6))
94 #define DPORT_CPU_WAIT_MODE_FORCE_ON (BIT(3))
95 #define DPORT_CPU_WAIT_MODE_FORCE_ON_M (BIT(3))
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Di2s_reg.h17 #define I2S_RX_RESET_ST (BIT(29))
18 #define I2S_RX_RESET_ST_M (BIT(29))
23 #define I2S_RX_BIG_ENDIAN (BIT(28))
24 #define I2S_RX_BIG_ENDIAN_M (BIT(28))
29 #define I2S_TX_BIG_ENDIAN (BIT(27))
30 #define I2S_TX_BIG_ENDIAN_M (BIT(27))
35 #define I2S_PRE_REQ_EN (BIT(26))
36 #define I2S_PRE_REQ_EN_M (BIT(26))
41 #define I2S_RX_DMA_EQUAL (BIT(25))
42 #define I2S_RX_DMA_EQUAL_M (BIT(25))
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/hal_espressif-latest/components/soc/esp32c2/include/soc/
Dspi_reg.h20 #define SPI_USR (BIT(24))
21 #define SPI_USR_M (BIT(24))
27 #define SPI_UPDATE (BIT(23))
28 #define SPI_UPDATE_M (BIT(23))
64 #define SPI_WP_POL (BIT(21))
65 #define SPI_WP_POL_M (BIT(21))
71 #define SPI_HOLD_POL (BIT(20))
72 #define SPI_HOLD_POL_M (BIT(20))
78 #define SPI_D_POL (BIT(19))
79 #define SPI_D_POL_M (BIT(19))
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Duart_reg.h27 #define UART_WAKEUP_INT_RAW (BIT(19))
28 #define UART_WAKEUP_INT_RAW_M (BIT(19))
34 #define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18))
35 #define UART_AT_CMD_CHAR_DET_INT_RAW_M (BIT(18))
41 #define UART_RS485_CLASH_INT_RAW (BIT(17))
42 #define UART_RS485_CLASH_INT_RAW_M (BIT(17))
48 #define UART_RS485_FRM_ERR_INT_RAW (BIT(16))
49 #define UART_RS485_FRM_ERR_INT_RAW_M (BIT(16))
55 #define UART_RS485_PARITY_ERR_INT_RAW (BIT(15))
56 #define UART_RS485_PARITY_ERR_INT_RAW_M (BIT(15))
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/hal_espressif-latest/components/esp_pm/
Dpm_trace.c19 BIT(4), BIT(5), // ESP_PM_TRACE_IDLE
20 BIT(16), BIT(17), // ESP_PM_TRACE_TICK
21 BIT(18), BIT(18), // ESP_PM_TRACE_FREQ_SWITCH
22 BIT(19), BIT(19), // ESP_PM_TRACE_CCOMPARE_UPDATE
23 BIT(25), BIT(26), // ESP_PM_TRACE_ISR_HOOK
24 BIT(27), BIT(27), // ESP_PM_TRACE_SLEEP
26 BIT(4), BIT(5), // ESP_PM_TRACE_IDLE
27 BIT(6), BIT(7), // ESP_PM_TRACE_TICK
28 BIT(14), BIT(14), // ESP_PM_TRACE_FREQ_SWITCH
29 BIT(15), BIT(15), // ESP_PM_TRACE_CCOMPARE_UPDATE
[all …]

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