Lines Matching refs:BIT
25 #define RMT_CONF_UPDATE_CH0 (BIT(24))
26 #define RMT_CONF_UPDATE_CH0_M (BIT(24))
31 #define RMT_AFIFO_RST_CH0 (BIT(23))
32 #define RMT_AFIFO_RST_CH0_M (BIT(23))
37 #define RMT_CARRIER_OUT_LV_CH0 (BIT(22))
38 #define RMT_CARRIER_OUT_LV_CH0_M (BIT(22))
43 #define RMT_CARRIER_EN_CH0 (BIT(21))
44 #define RMT_CARRIER_EN_CH0_M (BIT(21))
49 #define RMT_CARRIER_EFF_EN_CH0 (BIT(20))
50 #define RMT_CARRIER_EFF_EN_CH0_M (BIT(20))
67 #define RMT_TX_STOP_CH0 (BIT(7))
68 #define RMT_TX_STOP_CH0_M (BIT(7))
73 #define RMT_IDLE_OUT_EN_CH0 (BIT(6))
74 #define RMT_IDLE_OUT_EN_CH0_M (BIT(6))
79 #define RMT_IDLE_OUT_LV_CH0 (BIT(5))
80 #define RMT_IDLE_OUT_LV_CH0_M (BIT(5))
85 #define RMT_MEM_TX_WRAP_EN_CH0 (BIT(4))
86 #define RMT_MEM_TX_WRAP_EN_CH0_M (BIT(4))
91 #define RMT_TX_CONTI_MODE_CH0 (BIT(3))
92 #define RMT_TX_CONTI_MODE_CH0_M (BIT(3))
97 #define RMT_APB_MEM_RST_CH0 (BIT(2))
98 #define RMT_APB_MEM_RST_CH0_M (BIT(2))
103 #define RMT_MEM_RD_RST_CH0 (BIT(1))
104 #define RMT_MEM_RD_RST_CH0_M (BIT(1))
109 #define RMT_TX_START_CH0 (BIT(0))
110 #define RMT_TX_START_CH0_M (BIT(0))
117 #define RMT_CONF_UPDATE_CH1 (BIT(24))
118 #define RMT_CONF_UPDATE_CH1_M (BIT(24))
123 #define RMT_AFIFO_RST_CH1 (BIT(23))
124 #define RMT_AFIFO_RST_CH1_M (BIT(23))
129 #define RMT_CARRIER_OUT_LV_CH1 (BIT(22))
130 #define RMT_CARRIER_OUT_LV_CH1_M (BIT(22))
135 #define RMT_CARRIER_EN_CH1 (BIT(21))
136 #define RMT_CARRIER_EN_CH1_M (BIT(21))
141 #define RMT_CARRIER_EFF_EN_CH1 (BIT(20))
142 #define RMT_CARRIER_EFF_EN_CH1_M (BIT(20))
159 #define RMT_TX_STOP_CH1 (BIT(7))
160 #define RMT_TX_STOP_CH1_M (BIT(7))
165 #define RMT_IDLE_OUT_EN_CH1 (BIT(6))
166 #define RMT_IDLE_OUT_EN_CH1_M (BIT(6))
171 #define RMT_IDLE_OUT_LV_CH1 (BIT(5))
172 #define RMT_IDLE_OUT_LV_CH1_M (BIT(5))
177 #define RMT_MEM_TX_WRAP_EN_CH1 (BIT(4))
178 #define RMT_MEM_TX_WRAP_EN_CH1_M (BIT(4))
183 #define RMT_TX_CONTI_MODE_CH1 (BIT(3))
184 #define RMT_TX_CONTI_MODE_CH1_M (BIT(3))
189 #define RMT_APB_MEM_RST_CH1 (BIT(2))
190 #define RMT_APB_MEM_RST_CH1_M (BIT(2))
195 #define RMT_MEM_RD_RST_CH1 (BIT(1))
196 #define RMT_MEM_RD_RST_CH1_M (BIT(1))
201 #define RMT_TX_START_CH1 (BIT(0))
202 #define RMT_TX_START_CH1_M (BIT(0))
209 #define RMT_CARRIER_OUT_LV_CH2 (BIT(29))
210 #define RMT_CARRIER_OUT_LV_CH2_M (BIT(29))
215 #define RMT_CARRIER_EN_CH2 (BIT(28))
216 #define RMT_CARRIER_EN_CH2_M (BIT(28))
241 #define RMT_CONF_UPDATE_CH2 (BIT(15))
242 #define RMT_CONF_UPDATE_CH2_M (BIT(15))
247 #define RMT_AFIFO_RST_CH2 (BIT(14))
248 #define RMT_AFIFO_RST_CH2_M (BIT(14))
253 #define RMT_MEM_RX_WRAP_EN_CH2 (BIT(13))
254 #define RMT_MEM_RX_WRAP_EN_CH2_M (BIT(13))
265 #define RMT_RX_FILTER_EN_CH2 (BIT(4))
266 #define RMT_RX_FILTER_EN_CH2_M (BIT(4))
271 #define RMT_MEM_OWNER_CH2 (BIT(3))
272 #define RMT_MEM_OWNER_CH2_M (BIT(3))
277 #define RMT_APB_MEM_RST_CH2 (BIT(2))
278 #define RMT_APB_MEM_RST_CH2_M (BIT(2))
283 #define RMT_MEM_WR_RST_CH2 (BIT(1))
284 #define RMT_MEM_WR_RST_CH2_M (BIT(1))
289 #define RMT_RX_EN_CH2 (BIT(0))
290 #define RMT_RX_EN_CH2_M (BIT(0))
297 #define RMT_CARRIER_OUT_LV_CH3 (BIT(29))
298 #define RMT_CARRIER_OUT_LV_CH3_M (BIT(29))
303 #define RMT_CARRIER_EN_CH3 (BIT(28))
304 #define RMT_CARRIER_EN_CH3_M (BIT(28))
329 #define RMT_CONF_UPDATE_CH3 (BIT(15))
330 #define RMT_CONF_UPDATE_CH3_M (BIT(15))
335 #define RMT_AFIFO_RST_CH3 (BIT(14))
336 #define RMT_AFIFO_RST_CH3_M (BIT(14))
341 #define RMT_MEM_RX_WRAP_EN_CH3 (BIT(13))
342 #define RMT_MEM_RX_WRAP_EN_CH3_M (BIT(13))
353 #define RMT_RX_FILTER_EN_CH3 (BIT(4))
354 #define RMT_RX_FILTER_EN_CH3_M (BIT(4))
359 #define RMT_MEM_OWNER_CH3 (BIT(3))
360 #define RMT_MEM_OWNER_CH3_M (BIT(3))
365 #define RMT_APB_MEM_RST_CH3 (BIT(2))
366 #define RMT_APB_MEM_RST_CH3_M (BIT(2))
371 #define RMT_MEM_WR_RST_CH3 (BIT(1))
372 #define RMT_MEM_WR_RST_CH3_M (BIT(1))
377 #define RMT_RX_EN_CH3 (BIT(0))
378 #define RMT_RX_EN_CH3_M (BIT(0))
391 #define RMT_APB_MEM_WR_ERR_CH0 (BIT(23))
392 #define RMT_APB_MEM_WR_ERR_CH0_M (BIT(23))
397 #define RMT_MEM_EMPTY_CH0 (BIT(22))
398 #define RMT_MEM_EMPTY_CH0_M (BIT(22))
403 #define RMT_APB_MEM_RD_ERR_CH0 (BIT(21))
404 #define RMT_APB_MEM_RD_ERR_CH0_M (BIT(21))
435 #define RMT_APB_MEM_WR_ERR_CH1 (BIT(23))
436 #define RMT_APB_MEM_WR_ERR_CH1_M (BIT(23))
441 #define RMT_MEM_EMPTY_CH1 (BIT(22))
442 #define RMT_MEM_EMPTY_CH1_M (BIT(22))
447 #define RMT_APB_MEM_RD_ERR_CH1 (BIT(21))
448 #define RMT_APB_MEM_RD_ERR_CH1_M (BIT(21))
473 #define RMT_APB_MEM_RD_ERR_CH2 (BIT(27))
474 #define RMT_APB_MEM_RD_ERR_CH2_M (BIT(27))
479 #define RMT_MEM_FULL_CH2 (BIT(26))
480 #define RMT_MEM_FULL_CH2_M (BIT(26))
485 #define RMT_MEM_OWNER_ERR_CH2 (BIT(25))
486 #define RMT_MEM_OWNER_ERR_CH2_M (BIT(25))
511 #define RMT_APB_MEM_RD_ERR_CH3 (BIT(27))
512 #define RMT_APB_MEM_RD_ERR_CH3_M (BIT(27))
517 #define RMT_MEM_FULL_CH3 (BIT(26))
518 #define RMT_MEM_FULL_CH3_M (BIT(26))
523 #define RMT_MEM_OWNER_ERR_CH3 (BIT(25))
524 #define RMT_MEM_OWNER_ERR_CH3_M (BIT(25))
549 #define RMT_CH1_TX_LOOP_INT_RAW (BIT(13))
550 #define RMT_CH1_TX_LOOP_INT_RAW_M (BIT(13))
555 #define RMT_CH0_TX_LOOP_INT_RAW (BIT(12))
556 #define RMT_CH0_TX_LOOP_INT_RAW_M (BIT(12))
561 #define RMT_CH3_RX_THR_EVENT_INT_RAW (BIT(11))
562 #define RMT_CH3_RX_THR_EVENT_INT_RAW_M (BIT(11))
567 #define RMT_CH2_RX_THR_EVENT_INT_RAW (BIT(10))
568 #define RMT_CH2_RX_THR_EVENT_INT_RAW_M (BIT(10))
573 #define RMT_CH1_TX_THR_EVENT_INT_RAW (BIT(9))
574 #define RMT_CH1_TX_THR_EVENT_INT_RAW_M (BIT(9))
579 #define RMT_CH0_TX_THR_EVENT_INT_RAW (BIT(8))
580 #define RMT_CH0_TX_THR_EVENT_INT_RAW_M (BIT(8))
585 #define RMT_CH3_ERR_INT_RAW (BIT(7))
586 #define RMT_CH3_ERR_INT_RAW_M (BIT(7))
591 #define RMT_CH2_ERR_INT_RAW (BIT(6))
592 #define RMT_CH2_ERR_INT_RAW_M (BIT(6))
597 #define RMT_CH1_ERR_INT_RAW (BIT(5))
598 #define RMT_CH1_ERR_INT_RAW_M (BIT(5))
603 #define RMT_CH0_ERR_INT_RAW (BIT(4))
604 #define RMT_CH0_ERR_INT_RAW_M (BIT(4))
609 #define RMT_CH3_RX_END_INT_RAW (BIT(3))
610 #define RMT_CH3_RX_END_INT_RAW_M (BIT(3))
615 #define RMT_CH2_RX_END_INT_RAW (BIT(2))
616 #define RMT_CH2_RX_END_INT_RAW_M (BIT(2))
621 #define RMT_CH1_TX_END_INT_RAW (BIT(1))
622 #define RMT_CH1_TX_END_INT_RAW_M (BIT(1))
627 #define RMT_CH0_TX_END_INT_RAW (BIT(0))
628 #define RMT_CH0_TX_END_INT_RAW_M (BIT(0))
635 #define RMT_CH1_TX_LOOP_INT_ST (BIT(13))
636 #define RMT_CH1_TX_LOOP_INT_ST_M (BIT(13))
641 #define RMT_CH0_TX_LOOP_INT_ST (BIT(12))
642 #define RMT_CH0_TX_LOOP_INT_ST_M (BIT(12))
647 #define RMT_CH3_RX_THR_EVENT_INT_ST (BIT(11))
648 #define RMT_CH3_RX_THR_EVENT_INT_ST_M (BIT(11))
653 #define RMT_CH2_RX_THR_EVENT_INT_ST (BIT(10))
654 #define RMT_CH2_RX_THR_EVENT_INT_ST_M (BIT(10))
659 #define RMT_CH1_TX_THR_EVENT_INT_ST (BIT(9))
660 #define RMT_CH1_TX_THR_EVENT_INT_ST_M (BIT(9))
665 #define RMT_CH0_TX_THR_EVENT_INT_ST (BIT(8))
666 #define RMT_CH0_TX_THR_EVENT_INT_ST_M (BIT(8))
671 #define RMT_CH3_ERR_INT_ST (BIT(7))
672 #define RMT_CH3_ERR_INT_ST_M (BIT(7))
677 #define RMT_CH2_ERR_INT_ST (BIT(6))
678 #define RMT_CH2_ERR_INT_ST_M (BIT(6))
683 #define RMT_CH1_ERR_INT_ST (BIT(5))
684 #define RMT_CH1_ERR_INT_ST_M (BIT(5))
689 #define RMT_CH0_ERR_INT_ST (BIT(4))
690 #define RMT_CH0_ERR_INT_ST_M (BIT(4))
695 #define RMT_CH3_RX_END_INT_ST (BIT(3))
696 #define RMT_CH3_RX_END_INT_ST_M (BIT(3))
701 #define RMT_CH2_RX_END_INT_ST (BIT(2))
702 #define RMT_CH2_RX_END_INT_ST_M (BIT(2))
707 #define RMT_CH1_TX_END_INT_ST (BIT(1))
708 #define RMT_CH1_TX_END_INT_ST_M (BIT(1))
713 #define RMT_CH0_TX_END_INT_ST (BIT(0))
714 #define RMT_CH0_TX_END_INT_ST_M (BIT(0))
721 #define RMT_CH1_TX_LOOP_INT_ENA (BIT(13))
722 #define RMT_CH1_TX_LOOP_INT_ENA_M (BIT(13))
727 #define RMT_CH0_TX_LOOP_INT_ENA (BIT(12))
728 #define RMT_CH0_TX_LOOP_INT_ENA_M (BIT(12))
733 #define RMT_CH3_RX_THR_EVENT_INT_ENA (BIT(11))
734 #define RMT_CH3_RX_THR_EVENT_INT_ENA_M (BIT(11))
739 #define RMT_CH2_RX_THR_EVENT_INT_ENA (BIT(10))
740 #define RMT_CH2_RX_THR_EVENT_INT_ENA_M (BIT(10))
745 #define RMT_CH1_TX_THR_EVENT_INT_ENA (BIT(9))
746 #define RMT_CH1_TX_THR_EVENT_INT_ENA_M (BIT(9))
751 #define RMT_CH0_TX_THR_EVENT_INT_ENA (BIT(8))
752 #define RMT_CH0_TX_THR_EVENT_INT_ENA_M (BIT(8))
757 #define RMT_CH3_ERR_INT_ENA (BIT(7))
758 #define RMT_CH3_ERR_INT_ENA_M (BIT(7))
763 #define RMT_CH2_ERR_INT_ENA (BIT(6))
764 #define RMT_CH2_ERR_INT_ENA_M (BIT(6))
769 #define RMT_CH1_ERR_INT_ENA (BIT(5))
770 #define RMT_CH1_ERR_INT_ENA_M (BIT(5))
775 #define RMT_CH0_ERR_INT_ENA (BIT(4))
776 #define RMT_CH0_ERR_INT_ENA_M (BIT(4))
781 #define RMT_CH3_RX_END_INT_ENA (BIT(3))
782 #define RMT_CH3_RX_END_INT_ENA_M (BIT(3))
787 #define RMT_CH2_RX_END_INT_ENA (BIT(2))
788 #define RMT_CH2_RX_END_INT_ENA_M (BIT(2))
793 #define RMT_CH1_TX_END_INT_ENA (BIT(1))
794 #define RMT_CH1_TX_END_INT_ENA_M (BIT(1))
799 #define RMT_CH0_TX_END_INT_ENA (BIT(0))
800 #define RMT_CH0_TX_END_INT_ENA_M (BIT(0))
807 #define RMT_CH1_TX_LOOP_INT_CLR (BIT(13))
808 #define RMT_CH1_TX_LOOP_INT_CLR_M (BIT(13))
813 #define RMT_CH0_TX_LOOP_INT_CLR (BIT(12))
814 #define RMT_CH0_TX_LOOP_INT_CLR_M (BIT(12))
819 #define RMT_CH3_RX_THR_EVENT_INT_CLR (BIT(11))
820 #define RMT_CH3_RX_THR_EVENT_INT_CLR_M (BIT(11))
825 #define RMT_CH2_RX_THR_EVENT_INT_CLR (BIT(10))
826 #define RMT_CH2_RX_THR_EVENT_INT_CLR_M (BIT(10))
831 #define RMT_CH1_TX_THR_EVENT_INT_CLR (BIT(9))
832 #define RMT_CH1_TX_THR_EVENT_INT_CLR_M (BIT(9))
837 #define RMT_CH0_TX_THR_EVENT_INT_CLR (BIT(8))
838 #define RMT_CH0_TX_THR_EVENT_INT_CLR_M (BIT(8))
843 #define RMT_CH3_ERR_INT_CLR (BIT(7))
844 #define RMT_CH3_ERR_INT_CLR_M (BIT(7))
849 #define RMT_CH2_ERR_INT_CLR (BIT(6))
850 #define RMT_CH2_ERR_INT_CLR_M (BIT(6))
855 #define RMT_CH1_ERR_INT_CLR (BIT(5))
856 #define RMT_CH1_ERR_INT_CLR_M (BIT(5))
861 #define RMT_CH0_ERR_INT_CLR (BIT(4))
862 #define RMT_CH0_ERR_INT_CLR_M (BIT(4))
867 #define RMT_CH3_RX_END_INT_CLR (BIT(3))
868 #define RMT_CH3_RX_END_INT_CLR_M (BIT(3))
873 #define RMT_CH2_RX_END_INT_CLR (BIT(2))
874 #define RMT_CH2_RX_END_INT_CLR_M (BIT(2))
879 #define RMT_CH1_TX_END_INT_CLR (BIT(1))
880 #define RMT_CH1_TX_END_INT_CLR_M (BIT(1))
885 #define RMT_CH0_TX_END_INT_CLR (BIT(0))
886 #define RMT_CH0_TX_END_INT_CLR_M (BIT(0))
949 #define RMT_LOOP_COUNT_RESET_CH0 (BIT(20))
950 #define RMT_LOOP_COUNT_RESET_CH0_M (BIT(20))
955 #define RMT_TX_LOOP_CNT_EN_CH0 (BIT(19))
956 #define RMT_TX_LOOP_CNT_EN_CH0_M (BIT(19))
975 #define RMT_LOOP_COUNT_RESET_CH1 (BIT(20))
976 #define RMT_LOOP_COUNT_RESET_CH1_M (BIT(20))
981 #define RMT_TX_LOOP_CNT_EN_CH1 (BIT(19))
982 #define RMT_TX_LOOP_CNT_EN_CH1_M (BIT(19))
1017 #define RMT_CLK_EN (BIT(31))
1018 #define RMT_CLK_EN_M (BIT(31))
1023 #define RMT_SCLK_ACTIVE (BIT(26))
1024 #define RMT_SCLK_ACTIVE_M (BIT(26))
1053 #define RMT_MEM_FORCE_PU (BIT(3))
1054 #define RMT_MEM_FORCE_PU_M (BIT(3))
1059 #define RMT_MEM_FORCE_PD (BIT(2))
1060 #define RMT_MEM_FORCE_PD_M (BIT(2))
1065 #define RMT_MEM_CLK_FORCE_ON (BIT(1))
1066 #define RMT_MEM_CLK_FORCE_ON_M (BIT(1))
1071 #define RMT_APB_FIFO_MASK (BIT(0))
1072 #define RMT_APB_FIFO_MASK_M (BIT(0))
1079 #define RMT_TX_SIM_EN (BIT(2))
1080 #define RMT_TX_SIM_EN_M (BIT(2))
1085 #define RMT_TX_SIM_CH1 (BIT(1))
1086 #define RMT_TX_SIM_CH1_M (BIT(1))
1091 #define RMT_TX_SIM_CH0 (BIT(0))
1092 #define RMT_TX_SIM_CH0_M (BIT(0))
1099 #define RMT_REF_CNT_RST_CH3 (BIT(3))
1100 #define RMT_REF_CNT_RST_CH3_M (BIT(3))
1105 #define RMT_REF_CNT_RST_CH2 (BIT(2))
1106 #define RMT_REF_CNT_RST_CH2_M (BIT(2))
1111 #define RMT_REF_CNT_RST_CH1 (BIT(1))
1112 #define RMT_REF_CNT_RST_CH1_M (BIT(1))
1117 #define RMT_REF_CNT_RST_CH0 (BIT(0))
1118 #define RMT_REF_CNT_RST_CH0_M (BIT(0))