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Searched refs:APB_SARADC_CTRL_REG (Results 1 – 17 of 17) sorted by relevance

/hal_espressif-latest/components/bootloader_support/src/
Dbootloader_random_esp32c2.c33 SET_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_SAR_CLK_GATED_M); in bootloader_random_enable()
34 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_XPD_SAR_FORCE, 0x3); in bootloader_random_enable()
35 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR_CLK_DIV, 1); in bootloader_random_enable()
41 SET_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_SAR_PATT_P_CLEAR_M); in bootloader_random_enable()
42 CLEAR_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_SAR_PATT_P_CLEAR_M); in bootloader_random_enable()
43 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR_PATT_LEN, 0); in bootloader_random_enable()
65 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_XPD_SAR_FORCE, 0); in bootloader_random_disable()
Dbootloader_random_esp32c3.c33 SET_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_SAR_CLK_GATED_M); in bootloader_random_enable()
34 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_XPD_SAR_FORCE, 0x3); in bootloader_random_enable()
35 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR_CLK_DIV, 1); in bootloader_random_enable()
41 SET_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_SAR_PATT_P_CLEAR_M); in bootloader_random_enable()
42 CLEAR_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_SAR_PATT_P_CLEAR_M); in bootloader_random_enable()
43 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR_PATT_LEN, 0); in bootloader_random_enable()
65 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_XPD_SAR_FORCE, 0); in bootloader_random_disable()
Dbootloader_random_esp32s3.c33 SET_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_SAR_CLK_GATED); in bootloader_random_enable()
41 …REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR_CLK_DIV, 3); // SAR clock divider has to be at l… in bootloader_random_enable()
44 CLEAR_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_START_FORCE); in bootloader_random_enable()
47 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_WORK_MODE, 1); in bootloader_random_enable()
49 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR2_PATT_LEN, 0); in bootloader_random_enable()
51 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR1_PATT_LEN, 0); in bootloader_random_enable()
Dbootloader_random_esp32s2.c55 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR1_PATT_LEN, 0); in bootloader_random_enable()
58 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR2_PATT_LEN, 0); in bootloader_random_enable()
63 REG_SET_FIELD(APB_SARADC_CTRL_REG,APB_SARADC_WORK_MODE, 1); in bootloader_random_enable()
73 CLEAR_PERI_REG_MASK(APB_SARADC_CTRL_REG,APB_SARADC_START_FORCE); in bootloader_random_enable()
Dbootloader_random_esp32h2.c54 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SARADC_SAR_PATT_LEN, 0); in bootloader_random_enable()
57 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SARADC_SAR_CLK_DIV, 15); in bootloader_random_enable()
Dbootloader_random_esp32c6.c61 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SARADC_SAR_PATT_LEN, 1); in bootloader_random_enable()
64 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SARADC_SAR_CLK_DIV, 15); in bootloader_random_enable()
/hal_espressif-latest/zephyr/esp32c2/src/
Dsoc_random.c33 SET_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_SAR_CLK_GATED_M); in soc_random_enable()
34 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_XPD_SAR_FORCE, 0x3); in soc_random_enable()
35 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR_CLK_DIV, 1); in soc_random_enable()
41 SET_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_SAR_PATT_P_CLEAR_M); in soc_random_enable()
42 CLEAR_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_SAR_PATT_P_CLEAR_M); in soc_random_enable()
43 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR_PATT_LEN, 0); in soc_random_enable()
66 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_XPD_SAR_FORCE, 0); in soc_random_disable()
/hal_espressif-latest/zephyr/esp32c3/src/
Dsoc_random.c33 SET_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_SAR_CLK_GATED_M); in soc_random_enable()
34 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_XPD_SAR_FORCE, 0x3); in soc_random_enable()
35 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR_CLK_DIV, 1); in soc_random_enable()
41 SET_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_SAR_PATT_P_CLEAR_M); in soc_random_enable()
42 CLEAR_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_SAR_PATT_P_CLEAR_M); in soc_random_enable()
43 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR_PATT_LEN, 0); in soc_random_enable()
66 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_XPD_SAR_FORCE, 0); in soc_random_disable()
/hal_espressif-latest/zephyr/esp32s3/src/
Dsoc_random.c35 SET_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_SAR_CLK_GATED); in soc_random_enable()
46 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR_CLK_DIV, 3); in soc_random_enable()
49 CLEAR_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_START_FORCE); in soc_random_enable()
52 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_WORK_MODE, 1); in soc_random_enable()
55 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR2_PATT_LEN, 0); in soc_random_enable()
59 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR1_PATT_LEN, 0); in soc_random_enable()
/hal_espressif-latest/zephyr/esp32s2/src/
Dsoc_random.c50 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR1_PATT_LEN, 0); in soc_random_enable()
53 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR2_PATT_LEN, 0); in soc_random_enable()
58 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_WORK_MODE, 1); in soc_random_enable()
68 CLEAR_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_START_FORCE); in soc_random_enable()
/hal_espressif-latest/zephyr/esp32c6/src/
Dsoc_random.c67 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SARADC_SAR_PATT_LEN, 1); in soc_random_enable()
70 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SARADC_SAR_CLK_DIV, 15); in soc_random_enable()
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Dapb_saradc_reg.h22 #define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x000) macro
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Dapb_saradc_reg.h22 #define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x000) macro
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Dapb_saradc_reg.h23 #define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x0) macro
/hal_espressif-latest/components/soc/esp32c2/include/soc/
Dapb_saradc_reg.h17 #define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x0) macro
/hal_espressif-latest/components/soc/esp32h2/include/soc/
Dapb_saradc_reg.h17 #define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x0) macro
/hal_espressif-latest/components/soc/esp32c6/include/soc/
Dapb_saradc_reg.h17 #define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x0) macro