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Searched refs:APB_SARADC_CTRL2_REG (Results 1 – 17 of 17) sorted by relevance

/hal_espressif-latest/zephyr/esp32s2/src/
Dsoc_random.c60 CLEAR_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_MEAS_NUM_LIMIT); in soc_random_enable()
64 SET_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_SEL); in soc_random_enable()
66 REG_SET_FIELD(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_TARGET, 100); in soc_random_enable()
70 SET_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_EN); in soc_random_enable()
87 CLEAR_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_EN); in soc_random_disable()
/hal_espressif-latest/components/bootloader_support/src/
Dbootloader_random_esp32s2.c65 CLEAR_PERI_REG_MASK(APB_SARADC_CTRL2_REG,APB_SARADC_MEAS_NUM_LIMIT); in bootloader_random_enable()
69 SET_PERI_REG_MASK(APB_SARADC_CTRL2_REG,APB_SARADC_TIMER_SEL); in bootloader_random_enable()
71 REG_SET_FIELD(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_TARGET, 100); in bootloader_random_enable()
75 SET_PERI_REG_MASK(APB_SARADC_CTRL2_REG,APB_SARADC_TIMER_EN); in bootloader_random_enable()
92 CLEAR_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_EN); in bootloader_random_disable()
Dbootloader_random_esp32s3.c42 REG_SET_FIELD(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_TARGET, 70); in bootloader_random_enable()
46 CLEAR_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_MEAS_NUM_LIMIT); in bootloader_random_enable()
67 SET_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_SEL); in bootloader_random_enable()
68 SET_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_EN); in bootloader_random_enable()
91 CLEAR_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_EN); in bootloader_random_disable()
Dbootloader_random_esp32c2.c47 REG_SET_FIELD(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_TARGET, 100); in bootloader_random_enable()
49 CLEAR_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_MEAS_NUM_LIMIT); in bootloader_random_enable()
51 SET_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_EN); in bootloader_random_enable()
60 CLEAR_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_EN); in bootloader_random_disable()
Dbootloader_random_esp32c3.c47 REG_SET_FIELD(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_TARGET, 100); in bootloader_random_enable()
49 CLEAR_PERI_REG_MASK(APB_SARADC_CTRL2_REG,APB_SARADC_MEAS_NUM_LIMIT); in bootloader_random_enable()
51 SET_PERI_REG_MASK(APB_SARADC_CTRL2_REG,APB_SARADC_TIMER_EN); in bootloader_random_enable()
60 CLEAR_PERI_REG_MASK(APB_SARADC_CTRL2_REG,APB_SARADC_TIMER_EN); in bootloader_random_disable()
Dbootloader_random_esp32h2.c60 REG_SET_FIELD(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_TARGET, 200); in bootloader_random_enable()
63 REG_SET_BIT(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_EN); in bootloader_random_enable()
69 REG_CLR_BIT(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_EN); in bootloader_random_disable()
Dbootloader_random_esp32c6.c67 REG_SET_FIELD(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_TARGET, 200); in bootloader_random_enable()
70 REG_SET_BIT(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_EN); in bootloader_random_enable()
76 REG_CLR_BIT(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_EN); in bootloader_random_disable()
/hal_espressif-latest/zephyr/esp32s3/src/
Dsoc_random.c47 REG_SET_FIELD(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_TARGET, 70); in soc_random_enable()
51 CLEAR_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_MEAS_NUM_LIMIT); in soc_random_enable()
76 SET_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_SEL); in soc_random_enable()
77 SET_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_EN); in soc_random_enable()
99 CLEAR_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_EN); in soc_random_disable()
/hal_espressif-latest/zephyr/esp32c2/src/
Dsoc_random.c48 REG_SET_FIELD(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_TARGET, 100); in soc_random_enable()
50 CLEAR_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_MEAS_NUM_LIMIT); in soc_random_enable()
52 SET_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_EN); in soc_random_enable()
61 CLEAR_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_EN); in soc_random_disable()
/hal_espressif-latest/zephyr/esp32c3/src/
Dsoc_random.c48 REG_SET_FIELD(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_TARGET, 100); in soc_random_enable()
50 CLEAR_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_MEAS_NUM_LIMIT); in soc_random_enable()
52 SET_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_EN); in soc_random_enable()
61 CLEAR_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_EN); in soc_random_disable()
/hal_espressif-latest/zephyr/esp32c6/src/
Dsoc_random.c73 REG_SET_FIELD(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_TARGET, 200); in soc_random_enable()
76 REG_SET_BIT(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_EN); in soc_random_enable()
82 REG_CLR_BIT(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_EN); in soc_random_disable()
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Dapb_saradc_reg.h110 #define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x004) macro
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Dapb_saradc_reg.h72 #define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x004) macro
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Dapb_saradc_reg.h111 #define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x4) macro
/hal_espressif-latest/components/soc/esp32c2/include/soc/
Dapb_saradc_reg.h78 #define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x4) macro
/hal_espressif-latest/components/soc/esp32h2/include/soc/
Dapb_saradc_reg.h85 #define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x4) macro
/hal_espressif-latest/components/soc/esp32c6/include/soc/
Dapb_saradc_reg.h85 #define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x4) macro