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Searched refs:SYSTEM_CONTROL_CORE_1_RESETTING (Results 1 – 3 of 3) sorted by relevance

/hal_espressif-3.6.0/zephyr/esp32s3/src/boot/
Dapp_cpu_start.c34 REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETTING); in appcpu_start()
35 REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETTING); in appcpu_start()
/hal_espressif-3.6.0/components/esp_system/port/
Dcpu_start.c244 REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETTING); in start_other_core()
245 REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETTING); in start_other_core()
437 REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETTING);
/hal_espressif-3.6.0/components/soc/esp32s3/include/soc/
Dsystem_reg.h26 #define SYSTEM_CONTROL_CORE_1_RESETTING (BIT(2)) macro