/hal_espressif-3.6.0/components/soc/esp32s3/include/soc/ |
D | efuse_reg.h | 15 #define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) 23 #define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) 31 #define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) 39 #define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xC) 47 #define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) 55 #define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) 63 #define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) 71 #define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1C) 79 #define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) 87 #define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) [all …]
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D | soc.h | 38 #define DR_REG_EFUSE_BASE 0x60007000 macro
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/hal_espressif-3.6.0/components/soc/esp32/include/soc/ |
D | efuse_reg.h | 11 #define EFUSE_BLK0_RDATA0_REG (DR_REG_EFUSE_BASE + 0x000) 57 #define EFUSE_BLK0_RDATA1_REG (DR_REG_EFUSE_BASE + 0x004) 65 #define EFUSE_BLK0_RDATA2_REG (DR_REG_EFUSE_BASE + 0x008) 73 #define EFUSE_BLK0_RDATA3_REG (DR_REG_EFUSE_BASE + 0x00c) 143 #define EFUSE_BLK0_RDATA4_REG (DR_REG_EFUSE_BASE + 0x010) 196 #define EFUSE_BLK0_RDATA5_REG (DR_REG_EFUSE_BASE + 0x014) 250 #define EFUSE_BLK0_RDATA6_REG (DR_REG_EFUSE_BASE + 0x018) 316 #define EFUSE_BLK0_WDATA0_REG (DR_REG_EFUSE_BASE + 0x01c) 336 #define EFUSE_BLK0_WDATA1_REG (DR_REG_EFUSE_BASE + 0x020) 344 #define EFUSE_BLK0_WDATA2_REG (DR_REG_EFUSE_BASE + 0x024) [all …]
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D | soc.h | 63 #define DR_REG_EFUSE_BASE 0x3ff5A000 macro
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/hal_espressif-3.6.0/components/soc/esp32h2/include/soc/ |
D | efuse_reg.h | 22 #define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x000) 30 #define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x004) 157 #define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x008) 209 #define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0x00C) 266 #define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x010) 354 #define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x014) 362 #define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x018) 370 #define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x01C) 378 #define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x020) 386 #define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x024) [all …]
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D | soc.h | 71 #define DR_REG_EFUSE_BASE 0x6001A000 macro
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/hal_espressif-3.6.0/components/soc/esp32c3/include/soc/ |
D | efuse_reg.h | 14 #define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x000) 22 #define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x004) 149 #define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x008) 201 #define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0x00C) 258 #define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x010) 327 #define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x014) 335 #define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x018) 343 #define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x01C) 351 #define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x020) 359 #define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x024) [all …]
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D | soc.h | 56 #define DR_REG_EFUSE_BASE 0x60008800 macro
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/hal_espressif-3.6.0/components/esptool_py/esptool/espefuse/efuse/esp32s2/ |
D | mem_definition.py | 16 DR_REG_EFUSE_BASE = 0x3f41A000 variable in EfuseDefineRegisters 17 EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE 18 EFUSE_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020 19 EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x1c8 20 EFUSE_CONF_REG = DR_REG_EFUSE_BASE + 0x1cc 21 EFUSE_STATUS_REG = DR_REG_EFUSE_BASE + 0x1d0 22 EFUSE_CMD_REG = DR_REG_EFUSE_BASE + 0x1d4 23 EFUSE_RD_RS_ERR0_REG = DR_REG_EFUSE_BASE + 0x194 24 EFUSE_RD_RS_ERR1_REG = DR_REG_EFUSE_BASE + 0x198 25 EFUSE_RD_REPEAT_ERR0_REG = DR_REG_EFUSE_BASE + 0x17C [all …]
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/hal_espressif-3.6.0/components/soc/esp32s2/include/soc/ |
D | efuse_reg.h | 22 #define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x000) 30 #define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x004) 178 #define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x008) 283 #define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0x00c) 340 #define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x010) 415 #define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x014) 429 #define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x018) 437 #define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x01c) 445 #define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x020) 453 #define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x024) [all …]
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D | soc.h | 69 #define DR_REG_EFUSE_BASE 0x3f41A000 macro
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/hal_espressif-3.6.0/components/esptool_py/esptool/espefuse/efuse/esp32h2beta1/ |
D | mem_definition.py | 16 DR_REG_EFUSE_BASE = 0x6001A000 variable in EfuseDefineRegisters 17 EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE 18 EFUSE_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020 19 EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x1C8 20 EFUSE_CONF_REG = DR_REG_EFUSE_BASE + 0x1CC 21 EFUSE_STATUS_REG = DR_REG_EFUSE_BASE + 0x1D0 22 EFUSE_CMD_REG = DR_REG_EFUSE_BASE + 0x1D4 23 EFUSE_RD_RS_ERR0_REG = DR_REG_EFUSE_BASE + 0x1C0 24 EFUSE_RD_RS_ERR1_REG = DR_REG_EFUSE_BASE + 0x1C4 25 EFUSE_RD_REPEAT_ERR0_REG = DR_REG_EFUSE_BASE + 0x17C [all …]
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/hal_espressif-3.6.0/components/esptool_py/esptool/espefuse/efuse/esp32s3/ |
D | mem_definition.py | 17 DR_REG_EFUSE_BASE = 0x60007000 variable in EfuseDefineRegisters 18 EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE 19 EFUSE_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020 20 EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x1C8 21 EFUSE_CONF_REG = DR_REG_EFUSE_BASE + 0x1CC 22 EFUSE_STATUS_REG = DR_REG_EFUSE_BASE + 0x1D0 23 EFUSE_CMD_REG = DR_REG_EFUSE_BASE + 0x1D4 24 EFUSE_RD_RS_ERR0_REG = DR_REG_EFUSE_BASE + 0x1C0 25 EFUSE_RD_RS_ERR1_REG = DR_REG_EFUSE_BASE + 0x1C4 26 EFUSE_RD_REPEAT_ERR0_REG = DR_REG_EFUSE_BASE + 0x17C [all …]
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/hal_espressif-3.6.0/components/esptool_py/esptool/espefuse/efuse/esp32s3beta2/ |
D | mem_definition.py | 17 DR_REG_EFUSE_BASE = 0x6001A000 variable in EfuseDefineRegisters 18 EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE 19 EFUSE_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020 20 EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x1C8 21 EFUSE_CONF_REG = DR_REG_EFUSE_BASE + 0x1CC 22 EFUSE_STATUS_REG = DR_REG_EFUSE_BASE + 0x1D0 23 EFUSE_CMD_REG = DR_REG_EFUSE_BASE + 0x1D4 24 EFUSE_RD_RS_ERR0_REG = DR_REG_EFUSE_BASE + 0x1C0 25 EFUSE_RD_RS_ERR1_REG = DR_REG_EFUSE_BASE + 0x1C4 26 EFUSE_RD_REPEAT_ERR0_REG = DR_REG_EFUSE_BASE + 0x17C [all …]
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/hal_espressif-3.6.0/components/esptool_py/esptool/espefuse/efuse/esp32c6/ |
D | mem_definition.py | 16 DR_REG_EFUSE_BASE = 0x600B0800 variable in EfuseDefineRegisters 17 EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE 18 EFUSE_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020 19 EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x1C8 20 EFUSE_CONF_REG = DR_REG_EFUSE_BASE + 0x1CC 21 EFUSE_STATUS_REG = DR_REG_EFUSE_BASE + 0x1D0 22 EFUSE_CMD_REG = DR_REG_EFUSE_BASE + 0x1D4 23 EFUSE_RD_RS_ERR0_REG = DR_REG_EFUSE_BASE + 0x1C0 24 EFUSE_RD_RS_ERR1_REG = DR_REG_EFUSE_BASE + 0x1C4 25 EFUSE_RD_REPEAT_ERR0_REG = DR_REG_EFUSE_BASE + 0x17C [all …]
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/hal_espressif-3.6.0/components/esptool_py/esptool/espefuse/efuse/esp32h2/ |
D | mem_definition.py | 16 DR_REG_EFUSE_BASE = 0x600B0800 variable in EfuseDefineRegisters 17 EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE 18 EFUSE_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020 19 EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x1C8 20 EFUSE_CONF_REG = DR_REG_EFUSE_BASE + 0x1CC 21 EFUSE_STATUS_REG = DR_REG_EFUSE_BASE + 0x1D0 22 EFUSE_CMD_REG = DR_REG_EFUSE_BASE + 0x1D4 23 EFUSE_RD_RS_ERR0_REG = DR_REG_EFUSE_BASE + 0x1C0 24 EFUSE_RD_RS_ERR1_REG = DR_REG_EFUSE_BASE + 0x1C4 25 EFUSE_RD_REPEAT_ERR0_REG = DR_REG_EFUSE_BASE + 0x17C [all …]
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/hal_espressif-3.6.0/components/esptool_py/esptool/espefuse/efuse/esp32c3/ |
D | mem_definition.py | 16 DR_REG_EFUSE_BASE = 0x60008800 variable in EfuseDefineRegisters 17 EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE 18 EFUSE_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020 19 EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x1C8 20 EFUSE_CONF_REG = DR_REG_EFUSE_BASE + 0x1CC 21 EFUSE_STATUS_REG = DR_REG_EFUSE_BASE + 0x1D0 22 EFUSE_CMD_REG = DR_REG_EFUSE_BASE + 0x1D4 23 EFUSE_RD_RS_ERR0_REG = DR_REG_EFUSE_BASE + 0x1C0 24 EFUSE_RD_RS_ERR1_REG = DR_REG_EFUSE_BASE + 0x1C4 25 EFUSE_RD_REPEAT_ERR0_REG = DR_REG_EFUSE_BASE + 0x17C [all …]
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/hal_espressif-3.6.0/components/esptool_py/esptool/espefuse/efuse/esp32c2/ |
D | mem_definition.py | 16 DR_REG_EFUSE_BASE = 0x60008800 variable in EfuseDefineRegisters 17 EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE 18 EFUSE_PGM_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020 19 EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x88 20 EFUSE_CONF_REG = DR_REG_EFUSE_BASE + 0x8C 21 EFUSE_STATUS_REG = DR_REG_EFUSE_BASE + 0x90 22 EFUSE_CMD_REG = DR_REG_EFUSE_BASE + 0x94 23 EFUSE_RD_REPEAT_ERR_REG = DR_REG_EFUSE_BASE + 0x80 24 EFUSE_RD_RS_ERR_REG = DR_REG_EFUSE_BASE + 0x84 39 EFUSE_WR_TIM_CONF2_REG = DR_REG_EFUSE_BASE + 0x118 [all …]
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/hal_espressif-3.6.0/components/esptool_py/esptool/espefuse/efuse/esp32/ |
D | mem_definition.py | 14 DR_REG_EFUSE_BASE = 0x3FF5A000 variable in EfuseDefineRegisters 15 EFUSE_REG_CONF = DR_REG_EFUSE_BASE + 0x0FC 18 EFUSE_REG_CMD = DR_REG_EFUSE_BASE + 0x104 24 EFUSE_REG_DEC_STATUS = DR_REG_EFUSE_BASE + 0x11C 32 EFUSE_DAC_CONF_REG = DR_REG_EFUSE_BASE + 0x118 33 EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x0F8 52 EFUSE_BLK0_RDATA3_REG = DR_REG_EFUSE_BASE + 0x00C 55 EFUSE_BLK0_RDATA5_REG = DR_REG_EFUSE_BASE + 0x014 62 __base_regs = EfuseDefineRegisters.DR_REG_EFUSE_BASE
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/hal_espressif-3.6.0/components/esptool_py/esptool/espefuse/efuse/ |
D | emulate_efuse_controller_base.py | 58 self.mem.pos = self.mem.length - ((addr - self.REGS.DR_REG_EFUSE_BASE) * 8 + 32) 62 self.mem.pos = self.mem.length - ((addr - self.REGS.DR_REG_EFUSE_BASE) * 8 + 32) 67 position = self.mem.length - ((addr - self.REGS.DR_REG_EFUSE_BASE) * 8 + 32) 141 (addr - self.REGS.DR_REG_EFUSE_BASE) * 8 + blk_len_bits 153 (blk.rd_addr - self.REGS.DR_REG_EFUSE_BASE) * 8 + wr_data.len
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