DPORT_APP_CPU_DISABLED_CACHE_IA_DRAM1 (reference) in projects: hal_espressif-3.6.0

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Searched refs:DPORT_APP_CPU_DISABLED_CACHE_IA_DRAM1 (Results 1 – 2 of 2) sorted by relevance

/hal_espressif-3.6.0/components/esp_system/port/soc/esp32/
D	cache_err_int.c	`94 DPORT_APP_CPU_DISABLED_CACHE_IA_DRAM1 \| in esp_cache_err_get_cpuid()`
/hal_espressif-3.6.0/components/soc/esp32/include/soc/
D	dport_reg.h	`3057 #define DPORT_APP_CPU_DISABLED_CACHE_IA_DRAM1 BIT(10) macro`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
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babblesim_ext_2G4_channel_multiatt-3.4.0
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