1 /*
2 * Copyright (c) 2020 Mohamed ElShahawi.
3 * Copyright (c) 2021-2024 Espressif Systems (Shanghai) Co., Ltd.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #define DT_DRV_COMPAT espressif_esp32_rtc
9
10 #define CPU_RESET_REASON RTC_SW_CPU_RESET
11
12 #if defined(CONFIG_SOC_SERIES_ESP32)
13 #define DT_CPU_COMPAT espressif_xtensa_lx6
14 #undef CPU_RESET_REASON
15 #define CPU_RESET_REASON SW_CPU_RESET
16 #include <zephyr/dt-bindings/clock/esp32_clock.h>
17 #include <esp32/rom/rtc.h>
18 #include <soc/dport_reg.h>
19 #include <soc/i2s_reg.h>
20 #elif defined(CONFIG_SOC_SERIES_ESP32S2)
21 #define DT_CPU_COMPAT espressif_xtensa_lx7
22 #include <zephyr/dt-bindings/clock/esp32s2_clock.h>
23 #include <esp32s2/rom/rtc.h>
24 #include <soc/dport_reg.h>
25 #include <soc/i2s_reg.h>
26 #elif defined(CONFIG_SOC_SERIES_ESP32S3)
27 #define DT_CPU_COMPAT espressif_xtensa_lx7
28 #include <zephyr/dt-bindings/clock/esp32s3_clock.h>
29 #include <esp32s3/rom/rtc.h>
30 #include <soc/dport_reg.h>
31 #elif defined(CONFIG_SOC_SERIES_ESP32C2)
32 #define DT_CPU_COMPAT espressif_riscv
33 #include <zephyr/dt-bindings/clock/esp32c2_clock.h>
34 #include <esp32c2/rom/rtc.h>
35 #elif defined(CONFIG_SOC_SERIES_ESP32C3)
36 #define DT_CPU_COMPAT espressif_riscv
37 #include <zephyr/dt-bindings/clock/esp32c3_clock.h>
38 #include <esp32c3/rom/rtc.h>
39 #elif defined(CONFIG_SOC_SERIES_ESP32C6)
40 #define DT_CPU_COMPAT espressif_riscv
41 #include <zephyr/dt-bindings/clock/esp32c6_clock.h>
42 #include <soc/lp_clkrst_reg.h>
43 #include <soc/regi2c_dig_reg.h>
44 #include <regi2c_ctrl.h>
45 #include <esp32c6/rom/rtc.h>
46 #include <soc/dport_access.h>
47 #include <hal/clk_tree_ll.h>
48 #include <hal/usb_serial_jtag_ll.h>
49 #include <esp_private/esp_pmu.h>
50 #include <esp_private/esp_modem_clock.h>
51 #include <ocode_init.h>
52 #endif
53
54 #include <zephyr/drivers/clock_control.h>
55 #include <zephyr/drivers/clock_control/esp32_clock_control.h>
56
57 #include <esp_rom_caps.h>
58 #include <esp_rom_sys.h>
59 #include <esp_rom_uart.h>
60 #include <soc/periph_defs.h>
61 #include <soc/rtc.h>
62 #include <hal/clk_gate_ll.h>
63 #include <esp_private/periph_ctrl.h>
64 #include <esp_private/esp_clk.h>
65 #include <esp_cpu.h>
66 #include <hal/regi2c_ctrl_ll.h>
67 #include <hal/clk_tree_hal.h>
68 #include <esp_private/esp_clk_tree_common.h>
69
70 #include <zephyr/logging/log.h>
71 LOG_MODULE_REGISTER(clock_control, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
72
reset_reason_is_cpu_reset(void)73 static bool reset_reason_is_cpu_reset(void)
74 {
75 soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
76
77 if ((rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_SW ||
78 rst_reason == RESET_REASON_CPU0_RTC_WDT
79 #if !defined(CONFIG_SOC_SERIES_ESP32) && !defined(CONFIG_SOC_SERIES_ESP32C2)
80 || rst_reason == RESET_REASON_CPU0_MWDT1
81 #endif
82 )) {
83 return true;
84 }
85 return false;
86 }
87
88 #if defined(CONFIG_SOC_SERIES_ESP32C6)
esp32_clock_perip_init(void)89 static void esp32_clock_perip_init(void)
90 {
91 soc_rtc_slow_clk_src_t rtc_slow_clk_src = rtc_clk_slow_src_get();
92 modem_clock_lpclk_src_t modem_lpclk_src =
93 (modem_clock_lpclk_src_t)((rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW)
94 ? MODEM_CLOCK_LPCLK_SRC_RC_SLOW
95 : (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K)
96 ? MODEM_CLOCK_LPCLK_SRC_XTAL32K
97 : (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K)
98 ? MODEM_CLOCK_LPCLK_SRC_RC32K
99 : (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW)
100 ? MODEM_CLOCK_LPCLK_SRC_EXT32K
101 : SOC_RTC_SLOW_CLK_SRC_RC_SLOW);
102
103 modem_clock_select_lp_clock_source(PERIPH_WIFI_MODULE, modem_lpclk_src, 0);
104
105 soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
106
107 if ((rst_reason != RESET_REASON_CPU0_MWDT0) && (rst_reason != RESET_REASON_CPU0_MWDT1) &&
108 (rst_reason != RESET_REASON_CPU0_SW) && (rst_reason != RESET_REASON_CPU0_RTC_WDT)) {
109
110 periph_ll_disable_clk_set_rst(PERIPH_UART1_MODULE);
111 periph_ll_disable_clk_set_rst(PERIPH_I2C0_MODULE);
112 periph_ll_disable_clk_set_rst(PERIPH_RMT_MODULE);
113 periph_ll_disable_clk_set_rst(PERIPH_LEDC_MODULE);
114 periph_ll_disable_clk_set_rst(PERIPH_TIMG1_MODULE);
115 periph_ll_disable_clk_set_rst(PERIPH_TWAI0_MODULE);
116 periph_ll_disable_clk_set_rst(PERIPH_TWAI1_MODULE);
117 periph_ll_disable_clk_set_rst(PERIPH_I2S1_MODULE);
118 periph_ll_disable_clk_set_rst(PERIPH_PCNT_MODULE);
119 periph_ll_disable_clk_set_rst(PERIPH_ETM_MODULE);
120 periph_ll_disable_clk_set_rst(PERIPH_MCPWM0_MODULE);
121 periph_ll_disable_clk_set_rst(PERIPH_PARLIO_MODULE);
122 periph_ll_disable_clk_set_rst(PERIPH_GDMA_MODULE);
123 periph_ll_disable_clk_set_rst(PERIPH_SPI2_MODULE);
124 periph_ll_disable_clk_set_rst(PERIPH_TEMPSENSOR_MODULE);
125 periph_ll_disable_clk_set_rst(PERIPH_UHCI0_MODULE);
126 periph_ll_disable_clk_set_rst(PERIPH_SARADC_MODULE);
127 periph_ll_disable_clk_set_rst(PERIPH_SDIO_SLAVE_MODULE);
128 periph_ll_disable_clk_set_rst(PERIPH_RSA_MODULE);
129 periph_ll_disable_clk_set_rst(PERIPH_AES_MODULE);
130 periph_ll_disable_clk_set_rst(PERIPH_SHA_MODULE);
131 periph_ll_disable_clk_set_rst(PERIPH_ECC_MODULE);
132 periph_ll_disable_clk_set_rst(PERIPH_HMAC_MODULE);
133 periph_ll_disable_clk_set_rst(PERIPH_DS_MODULE);
134
135 REG_CLR_BIT(PCR_CTRL_TICK_CONF_REG, PCR_TICK_ENABLE);
136 REG_CLR_BIT(PCR_TRACE_CONF_REG, PCR_TRACE_CLK_EN);
137 REG_CLR_BIT(PCR_RETENTION_CONF_REG, PCR_RETENTION_CLK_EN);
138 REG_CLR_BIT(PCR_MEM_MONITOR_CONF_REG, PCR_MEM_MONITOR_CLK_EN);
139 REG_CLR_BIT(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
140 REG_CLR_BIT(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
141 WRITE_PERI_REG(PCR_CTRL_CLK_OUT_EN_REG, 0);
142
143 #if CONFIG_SERIAL_ESP32_USB
144 usb_serial_jtag_ll_enable_bus_clock(false);
145 #endif
146 }
147
148 if ((rst_reason == RESET_REASON_CHIP_POWER_ON) ||
149 (rst_reason == RESET_REASON_CHIP_BROWN_OUT) ||
150 (rst_reason == RESET_REASON_SYS_RTC_WDT) ||
151 (rst_reason == RESET_REASON_SYS_SUPER_WDT)) {
152
153 periph_ll_disable_clk_set_rst(PERIPH_LP_I2C0_MODULE);
154
155 CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_RNG_CK_EN);
156 CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_LP_UART_CK_EN);
157 CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_OTP_DBG_CK_EN);
158 CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_LP_EXT_I2C_CK_EN);
159 CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_LP_CPU_CK_EN);
160 WRITE_PERI_REG(LP_CLKRST_LP_CLK_PO_EN_REG, 0);
161 }
162 }
163 #else
164 #if !defined(CONFIG_SOC_ESP32_APPCPU) && !defined(CONFIG_SOC_ESP32S3_APPCPU)
esp32_clock_perip_init(void)165 static void esp32_clock_perip_init(void)
166 {
167 uint32_t common_perip_clk;
168 uint32_t hwcrypto_perip_clk;
169 uint32_t wifi_bt_sdio_clk;
170 #if !defined(CONFIG_SOC_SERIES_ESP32)
171 uint32_t common_perip_clk1;
172 #endif
173 /* For reason that only reset CPU, do not disable the clocks
174 * that have been enabled before reset.
175 */
176 if (reset_reason_is_cpu_reset()) {
177 #if defined(CONFIG_SOC_SERIES_ESP32C2) || \
178 defined(CONFIG_SOC_SERIES_ESP32C3) || \
179 defined(CONFIG_SOC_SERIES_ESP32S3)
180 common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG);
181 hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG);
182 wifi_bt_sdio_clk = ~READ_PERI_REG(SYSTEM_WIFI_CLK_EN_REG);
183 #else /* CONFIG_SOC_SERIES_ESP32 || CONFIG_SOC_SERIES_ESP32S2 */
184 common_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG);
185 hwcrypto_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERI_CLK_EN_REG);
186 wifi_bt_sdio_clk = ~DPORT_READ_PERI_REG(DPORT_WIFI_CLK_EN_REG);
187 #endif
188
189 #if defined(CONFIG_SOC_SERIES_ESP32S2)
190 hwcrypto_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN1_REG);
191 #endif
192 } else {
193 common_perip_clk =
194 #if defined(CONFIG_SOC_SERIES_ESP32C2)
195 SYSTEM_SPI2_CLK_EN |
196 #if ESP_CONSOLE_UART_NUM != 0
197 SYSTEM_UART_CLK_EN |
198 #endif
199 #if ESP_CONSOLE_UART_NUM != 1
200 SYSTEM_UART1_CLK_EN |
201 #endif
202 SYSTEM_LEDC_CLK_EN |
203 SYSTEM_I2C_EXT0_CLK_EN |
204 SYSTEM_LEDC_CLK_EN;
205 #elif (defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32S3))
206 SYSTEM_WDG_CLK_EN |
207 SYSTEM_I2S0_CLK_EN |
208 #if ESP_CONSOLE_UART_NUM != 0
209 SYSTEM_UART_CLK_EN |
210 #endif
211 #if ESP_CONSOLE_UART_NUM != 1
212 SYSTEM_UART1_CLK_EN |
213 #endif
214 #if defined(CONFIG_SOC_SERIES_ESP32S3)
215 #if ESP_CONSOLE_UART_NUM != 2
216 SYSTEM_UART2_CLK_EN |
217 #endif
218 SYSTEM_USB_CLK_EN |
219 SYSTEM_PCNT_CLK_EN |
220 SYSTEM_LEDC_CLK_EN |
221 SYSTEM_PWM0_CLK_EN |
222 SYSTEM_PWM1_CLK_EN |
223 SYSTEM_PWM2_CLK_EN |
224 SYSTEM_PWM3_CLK_EN |
225 #endif /* CONFIG_SOC_SERIES_ESP32S3 */
226 SYSTEM_SPI2_CLK_EN |
227 SYSTEM_I2C_EXT0_CLK_EN |
228 SYSTEM_UHCI0_CLK_EN |
229 SYSTEM_RMT_CLK_EN |
230 SYSTEM_LEDC_CLK_EN |
231 SYSTEM_TIMERGROUP1_CLK_EN |
232 SYSTEM_SPI3_CLK_EN |
233 SYSTEM_SPI4_CLK_EN |
234 SYSTEM_TWAI_CLK_EN |
235 SYSTEM_I2S1_CLK_EN |
236 SYSTEM_SPI2_DMA_CLK_EN |
237 SYSTEM_SPI3_DMA_CLK_EN;
238 #else /* CONFIG_SOC_SERIES_ESP32 || CONFIG_SOC_SERIES_ESP32S2 */
239 DPORT_WDG_CLK_EN |
240 DPORT_PCNT_CLK_EN |
241 DPORT_LEDC_CLK_EN |
242 DPORT_TIMERGROUP1_CLK_EN |
243 DPORT_PWM0_CLK_EN |
244 DPORT_TWAI_CLK_EN |
245 DPORT_PWM1_CLK_EN |
246 DPORT_PWM2_CLK_EN |
247 #if defined(CONFIG_SOC_SERIES_ESP32S2)
248 DPORT_I2S0_CLK_EN |
249 DPORT_SPI2_CLK_EN |
250 DPORT_I2C_EXT0_CLK_EN |
251 DPORT_UHCI0_CLK_EN |
252 DPORT_RMT_CLK_EN |
253 DPORT_SPI3_CLK_EN |
254 DPORT_PWM0_CLK_EN |
255 DPORT_TWAI_CLK_EN |
256 DPORT_I2S1_CLK_EN |
257 DPORT_SPI2_DMA_CLK_EN |
258 DPORT_SPI3_DMA_CLK_EN |
259 #endif /* CONFIG_SOC_SERIES_ESP32S2 */
260 DPORT_PWM3_CLK_EN;
261 #endif
262
263 #if !defined(CONFIG_SOC_SERIES_ESP32)
264 common_perip_clk1 = 0;
265 #endif
266 hwcrypto_perip_clk =
267 #if defined(CONFIG_SOC_SERIES_ESP32)
268 DPORT_PERI_EN_AES |
269 DPORT_PERI_EN_SHA |
270 DPORT_PERI_EN_RSA |
271 DPORT_PERI_EN_SECUREBOOT;
272 #endif /* CONFIG_SOC_SERIES_ESP32 */
273 #if defined(CONFIG_SOC_SERIES_ESP32S2)
274 DPORT_CRYPTO_AES_CLK_EN |
275 DPORT_CRYPTO_SHA_CLK_EN |
276 DPORT_CRYPTO_RSA_CLK_EN;
277 #endif /* CONFIG_SOC_SERIES_ESP32S2 */
278 #if defined(CONFIG_SOC_SERIES_ESP32C2)
279 SYSTEM_CRYPTO_SHA_CLK_EN;
280 #endif
281 #if (defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32S3))
282 SYSTEM_CRYPTO_AES_CLK_EN |
283 SYSTEM_CRYPTO_SHA_CLK_EN |
284 SYSTEM_CRYPTO_RSA_CLK_EN;
285 #endif /* CONFIG_SOC_SERIES_ESP32C3 || CONFIG_SOC_SERIES_ESP32S3 */
286
287 wifi_bt_sdio_clk =
288 #if defined(CONFIG_SOC_SERIES_ESP32C2)
289 SYSTEM_WIFI_CLK_WIFI_EN |
290 SYSTEM_WIFI_CLK_BT_EN_M |
291 SYSTEM_WIFI_CLK_UNUSED_BIT5 |
292 SYSTEM_WIFI_CLK_UNUSED_BIT12;
293 #elif (defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32S3))
294 SYSTEM_WIFI_CLK_WIFI_EN |
295 SYSTEM_WIFI_CLK_BT_EN_M |
296 SYSTEM_WIFI_CLK_I2C_CLK_EN |
297 #if defined(CONFIG_SOC_SERIES_ESP32S3)
298 SYSTEM_WIFI_CLK_SDIO_HOST_EN |
299 #endif /* CONFIG_SOC_SERIES_ESP32S3 */
300 SYSTEM_WIFI_CLK_UNUSED_BIT12;
301 #else /* CONFIG_SOC_SERIES_ESP32 || CONFIG_SOC_SERIES_ESP32S2 */
302 DPORT_WIFI_CLK_WIFI_EN |
303 DPORT_WIFI_CLK_BT_EN_M |
304 DPORT_WIFI_CLK_UNUSED_BIT5 |
305 DPORT_WIFI_CLK_UNUSED_BIT12 |
306 DPORT_WIFI_CLK_SDIOSLAVE_EN |
307 DPORT_WIFI_CLK_SDIO_HOST_EN |
308 DPORT_WIFI_CLK_EMAC_EN;
309 #endif /* CONFIG_SOC_SERIES_ESP32C3 */
310 }
311
312 /* Reset peripherals like I2C, SPI, UART, I2S and bring them to known state */
313 common_perip_clk |=
314 #if defined(CONFIG_SOC_SERIES_ESP32C2)
315 SYSTEM_SPI2_CLK_EN |
316 #if ESP_CONSOLE_UART_NUM != 0
317 SYSTEM_UART_CLK_EN |
318 #endif
319 #if ESP_CONSOLE_UART_NUM != 1
320 SYSTEM_UART1_CLK_EN |
321 #endif
322 SYSTEM_I2C_EXT0_CLK_EN;
323 #elif (defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32S3))
324 SYSTEM_I2S0_CLK_EN |
325 #if ESP_CONSOLE_UART_NUM != 0
326 SYSTEM_UART_CLK_EN |
327 #endif
328 #if ESP_CONSOLE_UART_NUM != 1
329 SYSTEM_UART1_CLK_EN |
330 #endif
331 #if defined(CONFIG_SOC_SERIES_ESP32S3)
332 #if ESP_CONSOLE_UART_NUM != 2
333 SYSTEM_UART2_CLK_EN |
334 #endif
335 SYSTEM_USB_CLK_EN |
336 #endif
337 SYSTEM_SPI2_CLK_EN |
338 SYSTEM_I2C_EXT0_CLK_EN |
339 SYSTEM_UHCI0_CLK_EN |
340 SYSTEM_RMT_CLK_EN |
341 SYSTEM_UHCI1_CLK_EN |
342 SYSTEM_SPI3_CLK_EN |
343 SYSTEM_SPI4_CLK_EN |
344 SYSTEM_I2C_EXT1_CLK_EN |
345 SYSTEM_I2S1_CLK_EN |
346 SYSTEM_SPI2_DMA_CLK_EN |
347 SYSTEM_SPI3_DMA_CLK_EN;
348 #else
349 DPORT_I2S0_CLK_EN |
350 DPORT_SPI2_CLK_EN |
351 DPORT_I2C_EXT0_CLK_EN |
352 DPORT_UHCI0_CLK_EN |
353 DPORT_RMT_CLK_EN |
354 DPORT_UHCI1_CLK_EN |
355 DPORT_SPI3_CLK_EN |
356 DPORT_I2C_EXT1_CLK_EN |
357 #if ESP_CONSOLE_UART_NUM != 0
358 DPORT_UART_CLK_EN |
359 #endif
360 #if ESP_CONSOLE_UART_NUM != 1
361 DPORT_UART1_CLK_EN |
362 #endif
363 #if defined(CONFIG_SOC_SERIES_ESP32)
364 DPORT_SPI_DMA_CLK_EN |
365 #if ESP_CONSOLE_UART_NUM != 2
366 DPORT_UART2_CLK_EN |
367 #endif
368 #endif /* CONFIG_SOC_SERIES_ESP32 */
369 #if defined(CONFIG_SOC_SERIES_ESP32S2)
370 DPORT_USB_CLK_EN |
371 DPORT_SPI2_DMA_CLK_EN |
372 DPORT_SPI3_DMA_CLK_EN |
373 #endif /* CONFIG_SOC_SERIES_ESP32S2 */
374 DPORT_I2S1_CLK_EN;
375 #endif /* CONFIG_SOC_SERIES_ESP32C3 */
376
377 #if !defined(CONFIG_SOC_SERIES_ESP32)
378 common_perip_clk1 = 0;
379 #endif
380
381 #if defined(CONFIG_SOC_SERIES_ESP32)
382 common_perip_clk &= ~DPORT_SPI01_CLK_EN;
383 #if defined(CONFIG_SPIRAM_SPEED_80M)
384 /*
385 * 80MHz SPIRAM uses SPI2/SPI3 as well; it's initialized before this is called. Because it
386 * is used in a weird mode where clock to the peripheral is disabled but reset is also
387 * disabled, it 'hangs' in a state where it outputs a continuous 80MHz signal. Mask its bit
388 * here because we should not modify that state, regardless of what we calculated earlier.
389 */
390 common_perip_clk &= ~DPORT_SPI2_CLK_EN;
391 common_perip_clk &= ~DPORT_SPI3_CLK_EN;
392 #endif
393 #endif /* CONFIG_SOC_SERIES_ESP32 */
394
395 /* Change I2S clock to audio PLL first. Because if I2S uses 160MHz clock,
396 * the current is not reduced when disable I2S clock.
397 */
398 #if defined(CONFIG_SOC_SERIES_ESP32)
399 DPORT_SET_PERI_REG_MASK(I2S_CLKM_CONF_REG(0), I2S_CLKA_ENA);
400 DPORT_SET_PERI_REG_MASK(I2S_CLKM_CONF_REG(1), I2S_CLKA_ENA);
401 #endif /* CONFIG_SOC_SERIES_ESP32 */
402 #if defined(CONFIG_SOC_SERIES_ESP32S2)
403 REG_SET_FIELD(I2S_CLKM_CONF_REG(0), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL);
404 REG_SET_FIELD(I2S_CLKM_CONF_REG(1), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL);
405 #endif /* CONFIG_SOC_SERIES_ESP32S2 */
406
407 /* Disable some peripheral clocks. */
408 #if defined(CONFIG_SOC_SERIES_ESP32C2) || \
409 defined(CONFIG_SOC_SERIES_ESP32C3) || \
410 defined(CONFIG_SOC_SERIES_ESP32S3)
411 CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, common_perip_clk);
412 SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, common_perip_clk);
413
414 CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, common_perip_clk1);
415 SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, common_perip_clk1);
416 #else /* CONFIG_SOC_SERIES_ESP32 || CONFIG_SOC_SERIES_ESP32S2 */
417 DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, common_perip_clk);
418 DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, common_perip_clk);
419 #endif /* CONFIG_SOC_SERIES_ESP32C3 || CONFIG_SOC_SERIES_ESP32S3 */
420
421 #if defined(CONFIG_SOC_SERIES_ESP32S2)
422 DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN1_REG, common_perip_clk1);
423 DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN1_REG, common_perip_clk1);
424 #endif
425
426 /* Disable hardware crypto clocks. */
427 #if defined(CONFIG_SOC_SERIES_ESP32C2) || \
428 defined(CONFIG_SOC_SERIES_ESP32C3) || \
429 defined(CONFIG_SOC_SERIES_ESP32S3)
430 CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, hwcrypto_perip_clk);
431 SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, hwcrypto_perip_clk);
432 #elif defined(CONFIG_SOC_SERIES_ESP32)
433 DPORT_CLEAR_PERI_REG_MASK(DPORT_PERI_CLK_EN_REG, hwcrypto_perip_clk);
434 DPORT_SET_PERI_REG_MASK(DPORT_PERI_RST_EN_REG, hwcrypto_perip_clk);
435 #elif defined(CONFIG_SOC_SERIES_ESP32S2)
436 DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN1_REG, hwcrypto_perip_clk);
437 DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN1_REG, hwcrypto_perip_clk);
438 #endif /* CONFIG_SOC_SERIES_ESP32C3 || CONFIG_SOC_SERIES_ESP32S3 */
439
440 #if defined(CONFIG_SOC_SERIES_ESP32S3)
441 /* Force clear backup dma reset signal. This is a fix to the backup dma
442 * implementation in the ROM, the reset signal was not cleared when the
443 * backup dma was started, which caused the backup dma operation to fail.
444 */
445 CLEAR_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_PERI_BACKUP_RST);
446 #endif /* CONFIG_SOC_SERIES_ESP32S3 */
447
448 /* Disable WiFi/BT/SDIO clocks. */
449 #if defined(CONFIG_SOC_SERIES_ESP32C2) || \
450 defined(CONFIG_SOC_SERIES_ESP32C3) || \
451 defined(CONFIG_SOC_SERIES_ESP32S3)
452 CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, wifi_bt_sdio_clk);
453 SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_EN);
454 #else /* CONFIG_SOC_SERIES_ESP32 || CONFIG_SOC_SERIES_ESP32S2 */
455 DPORT_CLEAR_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, wifi_bt_sdio_clk);
456 #endif /* CONFIG_SOC_SERIES_ESP32C3 || CONFIG_SOC_SERIES_ESP32S3 */
457
458 #if defined(CONFIG_SOC_SERIES_ESP32S2)
459 /* Enable WiFi MAC and POWER clocks */
460 DPORT_SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_WIFI_EN);
461 #endif
462
463 #if defined(CONFIG_SOC_SERIES_ESP32C2) || \
464 defined(CONFIG_SOC_SERIES_ESP32C3) || \
465 defined(CONFIG_SOC_SERIES_ESP32S3)
466 /* Set WiFi light sleep clock source to RTC slow clock */
467 REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0);
468 CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_8M);
469 SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW);
470 #elif defined(CONFIG_SOC_SERIES_ESP32S2)
471 /* Set WiFi light sleep clock source to RTC slow clock */
472 DPORT_REG_SET_FIELD(DPORT_BT_LPCK_DIV_INT_REG, DPORT_BT_LPCK_DIV_NUM, 0);
473 DPORT_CLEAR_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_8M);
474 DPORT_SET_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_RTC_SLOW);
475 #endif
476
477 /* Enable RNG clock. */
478 periph_module_enable(PERIPH_RNG_MODULE);
479
480 #if defined(CONFIG_SOC_SERIES_ESP32C2) || \
481 defined(CONFIG_SOC_SERIES_ESP32C3) || \
482 defined(CONFIG_SOC_SERIES_ESP32S3)
483 periph_module_enable(PERIPH_TIMG0_MODULE);
484 #endif
485 }
486 #endif
487 #endif
488
clock_control_esp32_get_status(const struct device * dev,clock_control_subsys_t sys)489 static enum clock_control_status clock_control_esp32_get_status(const struct device *dev,
490 clock_control_subsys_t sys)
491 {
492 ARG_UNUSED(dev);
493 uint32_t clk_en_reg = periph_ll_get_clk_en_reg((periph_module_t)sys);
494 uint32_t clk_en_mask = periph_ll_get_clk_en_mask((periph_module_t)sys);
495
496 if (DPORT_GET_PERI_REG_MASK(clk_en_reg, clk_en_mask)) {
497 return CLOCK_CONTROL_STATUS_ON;
498 }
499 return CLOCK_CONTROL_STATUS_OFF;
500 }
501
clock_control_esp32_on(const struct device * dev,clock_control_subsys_t sys)502 static int clock_control_esp32_on(const struct device *dev, clock_control_subsys_t sys)
503 {
504 enum clock_control_status status = clock_control_esp32_get_status(dev, sys);
505
506 if (status == CLOCK_CONTROL_STATUS_ON && !reset_reason_is_cpu_reset()) {
507 return -EALREADY;
508 }
509
510 periph_module_enable((periph_module_t)sys);
511
512 return 0;
513 }
514
clock_control_esp32_off(const struct device * dev,clock_control_subsys_t sys)515 static int clock_control_esp32_off(const struct device *dev, clock_control_subsys_t sys)
516 {
517 enum clock_control_status status = clock_control_esp32_get_status(dev, sys);
518
519 if (status == CLOCK_CONTROL_STATUS_ON) {
520 periph_module_disable((periph_module_t)sys);
521 }
522
523 return 0;
524 }
525
clock_control_esp32_get_rate(const struct device * dev,clock_control_subsys_t sys,uint32_t * rate)526 static int clock_control_esp32_get_rate(const struct device *dev, clock_control_subsys_t sys,
527 uint32_t *rate)
528 {
529 ARG_UNUSED(dev);
530
531 switch ((int)sys) {
532 case ESP32_CLOCK_CONTROL_SUBSYS_RTC_FAST:
533 *rate = esp_clk_tree_lp_fast_get_freq_hz(ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX);
534 break;
535 case ESP32_CLOCK_CONTROL_SUBSYS_RTC_SLOW:
536 *rate = clk_hal_lp_slow_get_freq_hz();
537 break;
538 default:
539 *rate = clk_hal_cpu_get_freq_hz();
540 }
541
542 return 0;
543 }
544
esp32_select_rtc_slow_clk(uint8_t slow_clk)545 static int esp32_select_rtc_slow_clk(uint8_t slow_clk)
546 {
547 #if !defined(CONFIG_SOC_SERIES_ESP32C6)
548 soc_rtc_slow_clk_src_t rtc_slow_clk_src = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V;
549 #else
550 soc_rtc_slow_clk_src_t rtc_slow_clk_src = slow_clk;
551 #endif
552 uint32_t cal_val = 0;
553 /* number of times to repeat 32k XTAL calibration
554 * before giving up and switching to the internal RC
555 */
556 int retry_32k_xtal = 3;
557
558 do {
559 #if defined(CONFIG_SOC_SERIES_ESP32C2)
560 if (rtc_slow_clk_src == ESP32_RTC_SLOW_CLK_SRC_OSC_SLOW) {
561 /* external clock needs to be connected to PIN0 before it can
562 * be used. Here we use rtc_clk_cal function to count
563 * the number of ext clk cycles in the given number of ext clk
564 * cycles. If the ext clk has not started up, calibration
565 * will time out, returning 0.
566 */
567 LOG_DBG("waiting for external clock by pin0 to start up");
568 rtc_clk_32k_enable_external();
569 #else
570 if (rtc_slow_clk_src == ESP32_RTC_SLOW_CLK_SRC_XTAL32K) {
571 /* 32k XTAL oscillator needs to be enabled and running before it can
572 * be used. Hardware doesn't have a direct way of checking if the
573 * oscillator is running. Here we use rtc_clk_cal function to count
574 * the number of main XTAL cycles in the given number of 32k XTAL
575 * oscillator cycles. If the 32k XTAL has not started up, calibration
576 * will time out, returning 0.
577 */
578 LOG_DBG("waiting for 32k oscillator to start up");
579 if (slow_clk == ESP32_RTC_SLOW_CLK_SRC_XTAL32K) {
580 rtc_clk_32k_enable(true);
581 } else if (slow_clk == ESP32_RTC_SLOW_CLK_32K_EXT_OSC) {
582 rtc_clk_32k_enable_external();
583 }
584 #endif
585 /* When CONFIG_RTC_CLK_CAL_CYCLES is set to 0, clock calibration will not be
586 * performed at startup.
587 */
588 if (CONFIG_RTC_CLK_CAL_CYCLES > 0) {
589 #if defined(CONFIG_SOC_SERIES_ESP32C2)
590 cal_val = rtc_clk_cal(RTC_CAL_32K_OSC_SLOW,
591 CONFIG_RTC_CLK_CAL_CYCLES);
592 #else
593 cal_val = rtc_clk_cal(RTC_CAL_32K_XTAL, CONFIG_RTC_CLK_CAL_CYCLES);
594 #endif
595 if (cal_val == 0) {
596 if (retry_32k_xtal-- > 0) {
597 continue;
598 }
599 LOG_ERR("32 kHz XTAL not found");
600 return -ENODEV;
601 }
602 }
603 #if defined(CONFIG_SOC_SERIES_ESP32C6)
604 } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) {
605 rtc_clk_rc32k_enable(true);
606 }
607 #else
608 } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
609 rtc_clk_8m_enable(true, true);
610 }
611 #endif
612 rtc_clk_slow_src_set(rtc_slow_clk_src);
613
614 if (CONFIG_RTC_CLK_CAL_CYCLES > 0) {
615 cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, CONFIG_RTC_CLK_CAL_CYCLES);
616 } else {
617 const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
618
619 cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz());
620 }
621 } while (cal_val == 0);
622
623 LOG_DBG("RTC_SLOW_CLK calibration value: %d", cal_val);
624
625 esp_clk_slowclk_cal_set(cal_val);
626
627 return 0;
628 }
629
esp32_cpu_clock_configure(const struct esp32_cpu_clock_config * cpu_cfg)630 static int esp32_cpu_clock_configure(const struct esp32_cpu_clock_config *cpu_cfg)
631 {
632 rtc_cpu_freq_config_t old_config;
633 rtc_cpu_freq_config_t new_config;
634 rtc_clk_config_t rtc_clk_cfg = RTC_CLK_CONFIG_DEFAULT();
635 bool ret;
636
637 rtc_clk_cfg.xtal_freq = cpu_cfg->xtal_freq;
638 rtc_clk_cfg.cpu_freq_mhz = cpu_cfg->cpu_freq;
639
640 esp_rom_uart_tx_wait_idle(ESP_CONSOLE_UART_NUM);
641
642 #if defined(CONFIG_SOC_SERIES_ESP32C6)
643 rtc_clk_modem_clock_domain_active_state_icg_map_preinit();
644
645 REG_SET_FIELD(LP_CLKRST_FOSC_CNTL_REG, LP_CLKRST_FOSC_DFREQ, rtc_clk_cfg.clk_8m_dfreq);
646 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_SCK_DCAP, rtc_clk_cfg.slow_clk_dcap);
647 REG_SET_FIELD(LP_CLKRST_RC32K_CNTL_REG, LP_CLKRST_RC32K_DFREQ, rtc_clk_cfg.rc32k_dfreq);
648 #else
649 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, rtc_clk_cfg.slow_clk_dcap);
650 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, rtc_clk_cfg.clk_8m_dfreq);
651 #endif
652
653 #if defined(CONFIG_SOC_SERIES_ESP32)
654 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL, rtc_clk_cfg.clk_8m_div - 1);
655 #elif defined(CONFIG_SOC_SERIES_ESP32C6)
656 clk_ll_rc_fast_tick_conf();
657 #else
658 /* Configure 150k clock division */
659 rtc_clk_divider_set(rtc_clk_cfg.clk_rtc_clk_div);
660
661 /* Configure 8M clock division */
662 rtc_clk_8m_divider_set(rtc_clk_cfg.clk_8m_clk_div);
663 #endif
664
665 #if !defined(CONFIG_SOC_SERIES_ESP32C6)
666 /* Reset (disable) i2c internal bus for all regi2c registers */
667 regi2c_ctrl_ll_i2c_reset();
668 /* Enable the internal bus used to configure BBPLL */
669 regi2c_ctrl_ll_i2c_bbpll_enable();
670 #endif
671
672 #if defined(CONFIG_SOC_SERIES_ESP32S2) || defined(CONFIG_SOC_SERIES_ESP32)
673 regi2c_ctrl_ll_i2c_apll_enable();
674 #endif
675
676 #if !defined(CONFIG_SOC_SERIES_ESP32S2)
677 rtc_clk_xtal_freq_update(rtc_clk_cfg.xtal_freq);
678 #endif
679 #if defined(CONFIG_SOC_SERIES_ESP32C6)
680 /* On ESP32C6, MSPI source clock's default HS divider leads to 120MHz,
681 * which is unusable before calibration. Therefore, before switching
682 * SOC_ROOT_CLK to HS, we need to set MSPI source clock HS divider
683 * to make it run at 80MHz after the switch. PLL = 480MHz, so divider is 6.
684 */
685 clk_ll_mspi_fast_set_hs_divider(6);
686 #else
687 rtc_clk_apb_freq_update(rtc_clk_cfg.xtal_freq * MHZ(1));
688 #endif
689
690 /* Set CPU frequency */
691 rtc_clk_cpu_freq_get_config(&old_config);
692
693 ret = rtc_clk_cpu_freq_mhz_to_config(rtc_clk_cfg.cpu_freq_mhz, &new_config);
694 if (!ret || (new_config.source != cpu_cfg->clk_src)) {
695 LOG_ERR("invalid CPU frequency value");
696 return -EINVAL;
697 }
698
699 rtc_clk_cpu_freq_set_config(&new_config);
700
701 /* Re-calculate the ccount to make time calculation correct. */
702 esp_cpu_set_cycle_count((uint64_t)esp_cpu_get_cycle_count() * rtc_clk_cfg.cpu_freq_mhz /
703 old_config.freq_mhz);
704
705 #if !defined(ESP_CONSOLE_UART_NONE)
706 #if !defined(CONFIG_SOC_SERIES_ESP32C2) && !defined(CONFIG_SOC_SERIES_ESP32C6)
707 #if defined(CONFIG_MCUBOOT) && defined(ESP_ROM_UART_CLK_IS_XTAL)
708 uint32_t uart_clock_src_hz = (uint32_t)rtc_clk_xtal_freq_get() * MHZ(1);
709 #else
710 uint32_t uart_clock_src_hz = esp_clk_apb_freq();
711 #endif
712 esp_rom_uart_set_clock_baudrate(ESP_CONSOLE_UART_NUM, uart_clock_src_hz,
713 ESP_CONSOLE_UART_BAUDRATE);
714 #endif
715 #endif
716 return 0;
717 }
718
clock_control_esp32_configure(const struct device * dev,clock_control_subsys_t sys,void * data)719 static int clock_control_esp32_configure(const struct device *dev, clock_control_subsys_t sys,
720 void *data)
721 {
722 struct esp32_clock_config *new_cfg = data;
723 int ret = 0;
724
725 switch ((int)sys) {
726 case ESP32_CLOCK_CONTROL_SUBSYS_RTC_FAST:
727 rtc_clk_fast_src_set(new_cfg->rtc.rtc_fast_clock_src);
728 break;
729 case ESP32_CLOCK_CONTROL_SUBSYS_RTC_SLOW:
730 ret = esp32_select_rtc_slow_clk(new_cfg->rtc.rtc_slow_clock_src);
731 break;
732 case ESP32_CLOCK_CONTROL_SUBSYS_CPU:
733 /* Normalize frequency */
734 new_cfg->cpu.xtal_freq = new_cfg->cpu.xtal_freq > MHZ(1)
735 ? new_cfg->cpu.xtal_freq / MHZ(1)
736 : new_cfg->cpu.xtal_freq;
737 new_cfg->cpu.cpu_freq = new_cfg->cpu.cpu_freq > MHZ(1)
738 ? new_cfg->cpu.cpu_freq / MHZ(1)
739 : new_cfg->cpu.cpu_freq;
740 ret = esp32_cpu_clock_configure(&new_cfg->cpu);
741 break;
742 default:
743 LOG_ERR("Unsupported subsystem %d", (int)sys);
744 return -EINVAL;
745 }
746 return ret;
747 }
748
clock_control_esp32_init(const struct device * dev)749 static int clock_control_esp32_init(const struct device *dev)
750 {
751 const struct esp32_clock_config *cfg = dev->config;
752 bool ret;
753 soc_reset_reason_t rst_reas;
754
755 rst_reas = esp_rom_get_reset_reason(0);
756
757 #if defined(CONFIG_SOC_SERIES_ESP32C6)
758 pmu_init();
759 if (rst_reas == RESET_REASON_CHIP_POWER_ON) {
760 esp_ocode_calib_init();
761 }
762 #else /* CONFIG_SOC_SERIES_ESP32C6 */
763 rtc_config_t rtc_cfg = RTC_CONFIG_DEFAULT();
764
765 #if !defined(CONFIG_SOC_SERIES_ESP32)
766 if (rst_reas == RESET_REASON_CHIP_POWER_ON
767 #if SOC_EFUSE_HAS_EFUSE_RST_BUG
768 || rst_reas == RESET_REASON_CORE_EFUSE_CRC
769 #endif /* SOC_EFUSE_HAS_EFUSE_RST_BUG */
770 ) {
771 rtc_cfg.cali_ocode = 1;
772 }
773 #endif /* !CONFIG_SOC_SERIES_ESP32 */
774 rtc_init(rtc_cfg);
775 #endif /* CONFIG_SOC_SERIES_ESP32C6 */
776
777 ret = esp32_cpu_clock_configure(&cfg->cpu);
778 if (ret) {
779 LOG_ERR("Failed to configure CPU clock");
780 return ret;
781 }
782
783 /* Prevent APPCPU from interfering with the clock setup */
784 #if !defined(CONFIG_SOC_ESP32_APPCPU) && !defined(CONFIG_SOC_ESP32S3_APPCPU)
785 rtc_clk_fast_src_set(cfg->rtc.rtc_fast_clock_src);
786
787 ret = esp32_select_rtc_slow_clk(cfg->rtc.rtc_slow_clock_src);
788 if (ret) {
789 LOG_ERR("Failed to configure RTC clock");
790 return ret;
791 }
792
793 esp32_clock_perip_init();
794 #endif
795
796 return 0;
797 }
798
799 static DEVICE_API(clock_control, clock_control_esp32_api) = {
800 .on = clock_control_esp32_on,
801 .off = clock_control_esp32_off,
802 .get_rate = clock_control_esp32_get_rate,
803 .get_status = clock_control_esp32_get_status,
804 .configure = clock_control_esp32_configure,
805 };
806
807 static const struct esp32_cpu_clock_config esp32_cpu_clock_config0 = {
808 .clk_src = DT_PROP(DT_INST(0, DT_CPU_COMPAT), clock_source),
809 .cpu_freq = (DT_PROP(DT_INST(0, DT_CPU_COMPAT), clock_frequency) / MHZ(1)),
810 .xtal_freq = ((DT_PROP(DT_INST(0, DT_CPU_COMPAT), xtal_freq)) / MHZ(1)),
811 };
812
813 static const struct esp32_rtc_clock_config esp32_rtc_clock_config0 = {
814 .rtc_fast_clock_src = DT_PROP(DT_INST(0, espressif_esp32_rtc), fast_clk_src),
815 .rtc_slow_clock_src = DT_PROP(DT_INST(0, espressif_esp32_rtc), slow_clk_src),
816 };
817
818 static const struct esp32_clock_config esp32_clock_config0 = {
819 .cpu = esp32_cpu_clock_config0,
820 .rtc = esp32_rtc_clock_config0
821 };
822
823 DEVICE_DT_DEFINE(DT_NODELABEL(rtc),
824 clock_control_esp32_init,
825 NULL,
826 NULL,
827 &esp32_clock_config0,
828 PRE_KERNEL_1,
829 CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
830 &clock_control_esp32_api);
831
