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Searched refs:GPIO_ENABLE_W1TS_REG (Results 1 – 10 of 10) sorted by relevance

/hal_espressif-3.5.0/components/esp_hw_support/test/
Dtest_unal_dma.c42 …SET_PERI_REG_MASK(GPIO_ENABLE_W1TS_REG, (1 << 11) | (1 << 3) | (1 << 0) | (1 << 2) | (1 << 5) | (1… in dmaMemcpy()
Dtest_ahb_arb.c47 …SET_PERI_REG_MASK(GPIO_ENABLE_W1TS_REG, (1 << 11) | (1 << 3) | (1 << 0) | (1 << 2) | (1 << 5) | (1… in lcdIfaceInit()
/hal_espressif-3.5.0/components/sdmmc/test/
Dtest_sd.c566 REG_WRITE(GPIO_ENABLE_W1TS_REG, BIT(gpio_cd_num)); in test_cd_input()
590 REG_WRITE(GPIO_ENABLE_W1TS_REG, BIT(gpio_wp_num)); in test_wp_input()
Dtest_sdio.c270 write_reg->addr = GPIO_ENABLE_W1TS_REG; in esp32_send_sip_command()
/hal_espressif-3.5.0/components/esp_hw_support/port/esp32h2/
Drtc_init.c225 SET_PERI_REG_MASK(GPIO_ENABLE_W1TS_REG, 1 << gpio_no); in dig_gpio_out_en()
/hal_espressif-3.5.0/components/soc/esp32c3/include/soc/
Dgpio_reg.h98 #define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x24) macro
/hal_espressif-3.5.0/components/soc/esp32h2/include/soc/
Dgpio_reg.h122 #define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x24) macro
/hal_espressif-3.5.0/components/soc/esp32/include/soc/
Dgpio_reg.h90 #define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x0024) macro
/hal_espressif-3.5.0/components/soc/esp32s2/include/soc/
Dgpio_reg.h122 #define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x24) macro
/hal_espressif-3.5.0/components/soc/esp32s3/include/soc/
Dgpio_reg.h125 #define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x24) macro