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Searched refs:DPORT_SOC_CLK_SEL_PLL (Results 1 – 9 of 9) sorted by relevance

/hal_espressif-3.5.0/components/esp_hw_support/port/esp32c3/
Drtc_clk.c286 REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_PLL); in rtc_clk_cpu_freq_to_pll_mhz()
337 if ((soc_clk_sel == DPORT_SOC_CLK_SEL_PLL) && !rtc_clk_set_bbpll_always_on()) { in rtc_clk_cpu_freq_set_config()
342 if (soc_clk_sel != DPORT_SOC_CLK_SEL_PLL) { in rtc_clk_cpu_freq_set_config()
349 if ((soc_clk_sel == DPORT_SOC_CLK_SEL_PLL) && !rtc_clk_set_bbpll_always_on()) { in rtc_clk_cpu_freq_set_config()
371 case DPORT_SOC_CLK_SEL_PLL: { in rtc_clk_cpu_freq_get_config()
Drtc_clk_common.h16 #define DPORT_SOC_CLK_SEL_PLL 1 macro
/hal_espressif-3.5.0/components/esp_hw_support/port/esp32s3/
Drtc_clk.c313 REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_PLL); in rtc_clk_cpu_freq_to_pll_mhz()
369 if ((soc_clk_sel == DPORT_SOC_CLK_SEL_PLL) && !rtc_clk_set_bbpll_always_on()) { in rtc_clk_cpu_freq_set_config()
374 if (soc_clk_sel != DPORT_SOC_CLK_SEL_PLL) { in rtc_clk_cpu_freq_set_config()
381 if ((soc_clk_sel == DPORT_SOC_CLK_SEL_PLL) && !rtc_clk_set_bbpll_always_on()) { in rtc_clk_cpu_freq_set_config()
403 case DPORT_SOC_CLK_SEL_PLL: { in rtc_clk_cpu_freq_get_config()
Drtc_clk_common.h20 #define DPORT_SOC_CLK_SEL_PLL 1 macro
/hal_espressif-3.5.0/components/esp_hw_support/port/esp32s2/
Drtc_clk.c293 REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_PLL); in rtc_clk_cpu_freq_to_pll_mhz()
350 if (soc_clk_sel == DPORT_SOC_CLK_SEL_PLL && config->source_freq_mhz != s_cur_pll_freq) { in rtc_clk_cpu_freq_set_config()
381 case DPORT_SOC_CLK_SEL_PLL: { in rtc_clk_cpu_freq_get_config()
Drtc_clk_common.h17 #define DPORT_SOC_CLK_SEL_PLL 1 macro
/hal_espressif-3.5.0/components/esp_hw_support/port/esp32h2/
Drtc_clk_common.h15 #define DPORT_SOC_CLK_SEL_PLL 1 macro
Drtc_clk.c193 rtc_clk_cpu_freq_set(DPORT_SOC_CLK_SEL_PLL, div - 1); in rtc_clk_cpu_freq_to_pll_mhz()
252 case DPORT_SOC_CLK_SEL_PLL: { in rtc_clk_cpu_freq_get_config()
/hal_espressif-3.5.0/components/soc/esp32s2/include/soc/
Dsystem_reg.h890 #define DPORT_SOC_CLK_SEL_PLL 1 macro