| /Zephyr-latest/drivers/clock_control/ |
| D | clock_control_mchp_xec.c | 280 const struct xec_pcr_config * const devcfg = dev->config; in soc_clk32_init() local
281 struct pcr_hw_regs *const pcr = (struct pcr_hw_regs *)devcfg->pcr_base; in soc_clk32_init()
282 struct vbatr_hw_regs *const vbr = (struct vbatr_hw_regs *)devcfg->vbr_base; in soc_clk32_init()
314 rc = pll_wait_lock_periph(pcr, devcfg->xtal_enable_delay_ms); in soc_clk32_init()
433 const struct xec_pcr_config * const devcfg = dev->config; in disable_32k_crystal() local
434 struct vbatr_hw_regs *const vbr = (struct vbatr_hw_regs *)devcfg->vbr_base; in disable_32k_crystal()
451 const struct xec_pcr_config * const devcfg = dev->config; in enable_32k_crystal() local
452 struct vbatr_hw_regs *const vbr = (struct vbatr_hw_regs *)devcfg->vbr_base; in enable_32k_crystal()
477 hib_timer_delay(HIBTIMER_MS_TO_CNT(devcfg->xtal_enable_delay_ms)); in enable_32k_crystal()
492 const struct xec_pcr_config * const devcfg = dev->config; in check_32k_crystal() local
[all …]
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| /Zephyr-latest/drivers/ps2/ |
| D | ps2_mchp_xec.c | 234 const struct ps2_xec_config *const devcfg = dev->config; in ps2_xec_pm_action() local
235 struct ps2_regs * const regs = devcfg->regs; in ps2_xec_pm_action()
240 if (devcfg->wakeup_source) { in ps2_xec_pm_action()
244 if (devcfg->wakerx_gpio.port != NULL) { in ps2_xec_pm_action()
246 &devcfg->wakerx_gpio, in ps2_xec_pm_action()
253 ps2_xec_girq_dis(devcfg->girq_id_wk, devcfg->girq_bit_wk); in ps2_xec_pm_action()
254 ps2_xec_girq_clr(devcfg->girq_id_wk, devcfg->girq_bit_wk); in ps2_xec_pm_action()
256 ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_DEFAULT); in ps2_xec_pm_action()
261 if (devcfg->wakeup_source) { in ps2_xec_pm_action()
265 ps2_xec_girq_clr(devcfg->girq_id_wk, devcfg->girq_bit_wk); in ps2_xec_pm_action()
[all …]
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| /Zephyr-latest/drivers/dma/ |
| D | dma_mchp_xec.c | 163 struct dma_xec_irq_info const *xec_chan_irq_info(const struct dma_xec_config *devcfg, in xec_chan_irq_info() argument
166 return &devcfg->irq_info_list[channel]; in xec_chan_irq_info()
210 const struct dma_xec_config * const devcfg = dev->config; in is_dma_config_valid() local
212 if (config->dma_slot >= (uint32_t)devcfg->dma_requests) { in is_dma_config_valid()
338 const struct dma_xec_config * const devcfg = dev->config; in dma_xec_configure() local
339 struct dma_xec_regs * const regs = devcfg->regs; in dma_xec_configure()
344 if (!config || (channel >= (uint32_t)devcfg->dma_channels)) { in dma_xec_configure()
352 const struct dma_xec_irq_info *info = xec_chan_irq_info(devcfg, channel); in dma_xec_configure()
454 const struct dma_xec_config * const devcfg = dev->config; in dma_xec_reload() local
456 struct dma_xec_regs * const regs = devcfg->regs; in dma_xec_reload()
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| /Zephyr-latest/drivers/pwm/ |
| D | pwm_mchp_xec_bbled.c | 271 const struct pwm_bbled_xec_config *const devcfg = dev->config; in pwm_bbled_xec_pm_action() local
272 struct bbled_regs * const regs = devcfg->regs; in pwm_bbled_xec_pm_action()
282 if ((!devcfg->enable_low_power_32K) && in pwm_bbled_xec_pm_action()
289 ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_DEFAULT); in pwm_bbled_xec_pm_action()
311 ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_SLEEP); in pwm_bbled_xec_pm_action()
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| D | pwm_mchp_xec.c | 380 const struct pwm_xec_config *const devcfg = dev->config; in pwm_xec_pm_action() local
381 struct pwm_regs * const regs = devcfg->regs; in pwm_xec_pm_action()
387 ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_DEFAULT); in pwm_xec_pm_action()
408 ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_SLEEP); in pwm_xec_pm_action()
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| /Zephyr-latest/drivers/adc/ |
| D | adc_mchp_xec.c | 111 const struct adc_xec_config * const devcfg = adc_dev->config; in adc_context_start_sampling() local
112 struct adc_xec_regs *regs = devcfg->regs; in adc_context_start_sampling()
373 const struct adc_xec_config *const devcfg = dev->config; in adc_xec_pm_action() local
374 struct adc_xec_regs * const adc_regs = devcfg->regs; in adc_xec_pm_action()
379 ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_DEFAULT); in adc_xec_pm_action()
389 ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_SLEEP); in adc_xec_pm_action()
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| /Zephyr-latest/drivers/spi/ |
| D | spi_xec_qmspi_ldma.c | 444 const struct spi_qmspi_config *devcfg = dev->config; in qmspi_xfr_cm_init() local
446 struct qmspi_regs *regs = devcfg->regs; in qmspi_xfr_cm_init()
534 const struct spi_qmspi_config *devcfg = dev->config; in q_ldma_cfg() local
537 struct qmspi_regs *regs = devcfg->regs; in q_ldma_cfg()
616 const struct spi_qmspi_config *devcfg = dev->config; in qmspi_xfr_sync() local
619 struct qmspi_regs *regs = devcfg->regs; in qmspi_xfr_sync()
677 const struct spi_qmspi_config *devcfg = dev->config; in qmspi_xfr_start_async() local
679 struct qmspi_regs *regs = devcfg->regs; in qmspi_xfr_start_async()
895 const struct spi_qmspi_config *devcfg = dev->config; in qmspi_xec_pm_action() local
900 ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_DEFAULT); in qmspi_xec_pm_action()
[all …]
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| /Zephyr-latest/drivers/eeprom/ |
| D | eeprom_mchp_xec.c | 307 const struct eeprom_xec_config *const devcfg = dev->config; in eeprom_xec_pm_action() local
308 struct eeprom_xec_regs * const regs = devcfg->regs; in eeprom_xec_pm_action()
313 ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_DEFAULT); in eeprom_xec_pm_action()
323 ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_SLEEP); in eeprom_xec_pm_action()
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| /Zephyr-latest/drivers/peci/ |
| D | peci_mchp_xec.c | 447 const struct peci_xec_config *const devcfg = dev->config; in peci_xec_pm_action() local
448 struct peci_regs * const regs = devcfg->regs; in peci_xec_pm_action()
454 ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_DEFAULT); in peci_xec_pm_action()
471 ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_SLEEP); in peci_xec_pm_action()
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