RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (reference) in projects: hal_espressif-3.4.0

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Searched refs:RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (Results 1 – 10 of 10) sorted by relevance

/hal_espressif-3.4.0/components/esp_hw_support/port/esp32c3/
D	rtc_sleep.c	`141 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES); in rtc_sleep_low_init()`
/hal_espressif-3.4.0/components/esp_hw_support/port/esp32s2/
D	rtc_sleep.c	`141 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES); in rtc_sleep_low_init()`
/hal_espressif-3.4.0/components/esp_hw_support/port/esp32s3/
D	rtc_sleep.c	`151 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES); in rtc_sleep_low_init()`
/hal_espressif-3.4.0/components/soc/esp32/include/soc/
D	rtc.h	`554 #define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1) macro`
/hal_espressif-3.4.0/components/esp_hw_support/port/esp32/
D	rtc_sleep.c	`209 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES); in rtc_sleep_low_init()`
/hal_espressif-3.4.0/components/esp_hw_support/port/esp32h2/
D	rtc_sleep.c	`221 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES); in rtc_sleep_low_init()`
/hal_espressif-3.4.0/components/soc/esp32s2/include/soc/
D	rtc.h	`110 #define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1) macro`
/hal_espressif-3.4.0/components/soc/esp32c3/include/soc/
D	rtc.h	`101 #define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1) macro`
/hal_espressif-3.4.0/components/soc/esp32s3/include/soc/
D	rtc.h	`106 #define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1) macro`
/hal_espressif-3.4.0/components/soc/esp32h2/include/soc/
D	rtc.h	`128 #define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1) macro`

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TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
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Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
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babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
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