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Searched refs:REG_GET_FIELD (Results 1 – 25 of 61) sorted by relevance

123

/hal_espressif-3.4.0/components/hal/esp32c3/include/hal/
Dmemprot_ll.h207 …uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_… in memprot_ll_iram0_get_pms_area_0()
213 …uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_… in memprot_ll_iram0_get_pms_area_1()
219 …uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_… in memprot_ll_iram0_get_pms_area_2()
225 …uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_… in memprot_ll_iram0_get_pms_area_3()
261 …return REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_… in memprot_ll_iram0_get_monitor_en()
282 …return REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_… in memprot_ll_iram0_get_monitor_status_intr()
287 …return REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_… in memprot_ll_iram0_get_monitor_status_fault_wr()
292 …return REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_… in memprot_ll_iram0_get_monitor_status_fault_loadstore()
297 …return REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_… in memprot_ll_iram0_get_monitor_status_fault_world()
302 …uint32_t addr = REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS… in memprot_ll_iram0_get_monitor_status_fault_addr()
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/hal_espressif-3.4.0/components/hal/esp32h2/include/hal/
Dmemprot_ll.h219 …uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_… in memprot_ll_iram0_get_pms_area_0()
225 …uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_… in memprot_ll_iram0_get_pms_area_1()
231 …uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_… in memprot_ll_iram0_get_pms_area_2()
237 …uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_… in memprot_ll_iram0_get_pms_area_3()
269 …return REG_GET_FIELD( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR… in memprot_ll_iram0_get_monitor_en()
290 …return REG_GET_FIELD( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR… in memprot_ll_iram0_get_monitor_status_intr()
295 …return REG_GET_FIELD( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR… in memprot_ll_iram0_get_monitor_status_fault_wr()
300 …return REG_GET_FIELD( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR… in memprot_ll_iram0_get_monitor_status_fault_loadstore()
305 …return REG_GET_FIELD( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR… in memprot_ll_iram0_get_monitor_status_fault_world()
310 …uint32_t addr = REG_GET_FIELD( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PM… in memprot_ll_iram0_get_monitor_status_fault_addr()
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/hal_espressif-3.4.0/components/esp_hw_support/port/esp32h2/
Drtc_clk.c114 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); in rtc_clk_slow_freq_get()
135 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); in rtc_clk_fast_freq_get()
243 uint32_t soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL); in rtc_clk_cpu_freq_get_config()
247 div = REG_GET_FIELD(SYSTEM_CPUCLK_CONF_REG, SYSTEM_PRE_DIV_CNT) + 1; in rtc_clk_cpu_freq_get_config()
254 div = REG_GET_FIELD(SYSTEM_CPUCLK_CONF_REG, SYSTEM_PRE_DIV_CNT) + 1; in rtc_clk_cpu_freq_get_config()
262 div = REG_GET_FIELD(SYSTEM_CPUCLK_CONF_REG, SYSTEM_PRE_DIV_CNT) + 1; in rtc_clk_cpu_freq_get_config()
268 div = REG_GET_FIELD(SYSTEM_CPUCLK_CONF_REG, SYSTEM_PRE_DIV_CNT) + 1; in rtc_clk_cpu_freq_get_config()
349 uint32_t apb_div = REG_GET_FIELD(SYSTEM_BUSCLK_CONF_REG, SYSTEM_APB_DIV_NUM) + 1; in rtc_clk_apb_freq_get()
356 uint32_t ahb_div = REG_GET_FIELD(SYSTEM_BUSCLK_CONF_REG, SYSTEM_AHB_DIV_NUM) + 1; in rtc_clk_ahb_freq_get()
409 return REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SPLL_FREQ); in read_spll_freq()
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/hal_espressif-3.4.0/components/esp_adc_cal/esp32/
Desp_adc_cal.c103 return (REG_GET_FIELD(VREF_REG, EFUSE_RD_ADC_VREF) != 0) ? true : false; in check_efuse_vref()
109 if (CHECK_BLK3_FLAG && (REG_GET_FIELD(BLK3_RESERVED_REG, EFUSE_RD_BLK3_PART_RESERVE) == 0)) { in check_efuse_tp()
113 if ((REG_GET_FIELD(TP_REG, EFUSE_RD_ADC1_TP_LOW) != 0) && in check_efuse_tp()
114 (REG_GET_FIELD(TP_REG, EFUSE_RD_ADC2_TP_LOW) != 0) && in check_efuse_tp()
115 (REG_GET_FIELD(TP_REG, EFUSE_RD_ADC1_TP_HIGH) != 0) && in check_efuse_tp()
116 (REG_GET_FIELD(TP_REG, EFUSE_RD_ADC2_TP_HIGH) != 0)) { in check_efuse_tp()
144 uint32_t bits = REG_GET_FIELD(VREF_REG, EFUSE_ADC_VREF); in read_efuse_vref()
157 bits = REG_GET_FIELD(TP_REG, EFUSE_RD_ADC1_TP_LOW); in read_efuse_tp_low()
160 bits = REG_GET_FIELD(TP_REG, EFUSE_RD_ADC2_TP_LOW); in read_efuse_tp_low()
174 bits = REG_GET_FIELD(TP_REG, EFUSE_RD_ADC1_TP_HIGH); in read_efuse_tp_high()
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/hal_espressif-3.4.0/zephyr/esp32/src/esp_adc_cal/
Desp_adc_cal.c102 return (REG_GET_FIELD(VREF_REG, EFUSE_RD_ADC_VREF) != 0) ? true : false; in check_efuse_vref()
108 if (CHECK_BLK3_FLAG && (REG_GET_FIELD(BLK3_RESERVED_REG, EFUSE_RD_BLK3_PART_RESERVE) == 0)) { in check_efuse_tp()
112 if ((REG_GET_FIELD(TP_REG, EFUSE_RD_ADC1_TP_LOW) != 0) && in check_efuse_tp()
113 (REG_GET_FIELD(TP_REG, EFUSE_RD_ADC2_TP_LOW) != 0) && in check_efuse_tp()
114 (REG_GET_FIELD(TP_REG, EFUSE_RD_ADC1_TP_HIGH) != 0) && in check_efuse_tp()
115 (REG_GET_FIELD(TP_REG, EFUSE_RD_ADC2_TP_HIGH) != 0)) { in check_efuse_tp()
143 uint32_t bits = REG_GET_FIELD(VREF_REG, EFUSE_ADC_VREF); in read_efuse_vref()
156 bits = REG_GET_FIELD(TP_REG, EFUSE_RD_ADC1_TP_LOW); in read_efuse_tp_low()
159 bits = REG_GET_FIELD(TP_REG, EFUSE_RD_ADC2_TP_LOW); in read_efuse_tp_low()
173 bits = REG_GET_FIELD(TP_REG, EFUSE_RD_ADC1_TP_HIGH); in read_efuse_tp_high()
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/hal_espressif-3.4.0/components/hal/esp32s3/include/hal/
Drtc_cntl_ll.h40 return REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_STATUS_REG, RTC_CNTL_EXT_WAKEUP1_STATUS); in rtc_cntl_ll_ext1_get_wakeup_pins()
68 uint32_t target = REG_GET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET); in rtc_cntl_ll_enable_tagmem_retention()
91 uint32_t target = REG_GET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET); in rtc_cntl_ll_disable_tagmem_retention()
117 uint32_t target = REG_GET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET); in rtc_cntl_ll_enable_cpu_retention()
/hal_espressif-3.4.0/components/esp_hw_support/port/esp32c3/
Drtc_clk.c135 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); in rtc_clk_slow_freq_get()
156 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); in rtc_clk_fast_freq_get()
334 uint32_t soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL); in rtc_clk_cpu_freq_set_config()
362 uint32_t soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL); in rtc_clk_cpu_freq_get_config()
366 div = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT) + 1; in rtc_clk_cpu_freq_get_config()
373 uint32_t cpuperiod_sel = REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL); in rtc_clk_cpu_freq_get_config()
374 uint32_t pllfreq_sel = REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL); in rtc_clk_cpu_freq_get_config()
Drtc_time.c53 int dig_32k_xtal_state = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN); in rtc_clk_cal_internal()
102 cal_val = REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_VALUE); in rtc_clk_cal_internal()
/hal_espressif-3.4.0/components/esp_hw_support/port/esp32s2/
Drtc_time.c83 cal_val = REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_VALUE); in rtc_clk_cal_internal_oneoff()
105 in_calibration_clk = REG_GET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL); in rtc_clk_cal_internal_cycling()
106 uint32_t cali_slowclk_cycles = REG_GET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX); in rtc_clk_cal_internal_cycling()
118 uint32_t cal_val = REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_VALUE); in rtc_clk_cal_internal_cycling()
163 int dig_32k_xtal_state = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN); in rtc_clk_cal_internal()
Dregi2c_ctrl.c111 return REG_GET_FIELD(I2C_RTC_CONFIG2, I2C_RTC_DATA); in i2c_rtc_read_reg()
123 uint32_t data = REG_GET_FIELD(I2C_RTC_CONFIG2, I2C_RTC_DATA); in i2c_rtc_read_reg_mask()
149 temp = REG_GET_FIELD(I2C_RTC_CONFIG2, I2C_RTC_DATA); in i2c_rtc_write_reg_mask()
Drtc_clk.c172 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); in rtc_clk_slow_freq_get()
193 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); in rtc_clk_fast_freq_get()
346 uint32_t soc_clk_sel = REG_GET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL); in rtc_clk_cpu_freq_set_config()
372 uint32_t soc_clk_sel = REG_GET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL); in rtc_clk_cpu_freq_get_config()
376 div = REG_GET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT) + 1; in rtc_clk_cpu_freq_get_config()
/hal_espressif-3.4.0/components/soc/src/esp32/
Drtc_clk.c90 #define RTC_CNTL_DBIAS_HP_VOLT (RTC_CNTL_DBIAS_1V25 - (REG_GET_FIELD(EFUSE_BLK0_RDATA5_REG,…
242 REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL) != RTC_CNTL_SOC_CLK_SEL_PLL) { in rtc_clk_apll_enable()
288 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); in rtc_clk_slow_freq_get()
309 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); in rtc_clk_fast_freq_get()
454 uint32_t apll_fpd = REG_GET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD); in rtc_clk_bbpll_disable()
612 uint32_t soc_clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL); in rtc_clk_cpu_freq_set_config()
640 uint32_t soc_clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL); in rtc_clk_cpu_freq_get_config()
644 div = REG_GET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT) + 1; in rtc_clk_cpu_freq_get_config()
/hal_espressif-3.4.0/components/bootloader_support/src/
Dbootloader_efuse_esp32c3.c13 return REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_WAFER_VERSION); in bootloader_common_get_chip_revision()
19 return REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_PKG_VERSION); in bootloader_common_get_chip_ver_pkg()
Dbootloader_efuse_esp32h2.c13 return REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_WAFER_VERSION); in bootloader_common_get_chip_revision()
19 return REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_PKG_VERSION); in bootloader_common_get_chip_ver_pkg()
Dbootloader_efuse_esp32s2.c15 return REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_WAFER_VERSION); in bootloader_common_get_chip_revision()
21 return REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_4_REG, EFUSE_PKG_VERSION); in bootloader_common_get_chip_ver_pkg()
Dbootloader_efuse_esp32.c47 uint32_t pkg_version = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG); in bootloader_common_get_chip_ver_pkg()
48 uint32_t pkg_version_4bit = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG_4BIT); in bootloader_common_get_chip_ver_pkg()
/hal_espressif-3.4.0/components/esp_hw_support/port/esp32/
Drtc_clk.c85 #define RTC_CNTL_DBIAS_HP_VOLT (RTC_CNTL_DBIAS_1V25 - (REG_GET_FIELD(EFUSE_BLK0_RDATA5_REG,…
277 REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL) != RTC_CNTL_SOC_CLK_SEL_PLL) { in rtc_clk_apll_enable()
323 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); in rtc_clk_slow_freq_get()
344 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); in rtc_clk_fast_freq_get()
489 uint32_t apll_fpd = REG_GET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD); in rtc_clk_bbpll_disable()
647 uint32_t soc_clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL); in rtc_clk_cpu_freq_set_config()
675 uint32_t soc_clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL); in rtc_clk_cpu_freq_get_config()
679 div = REG_GET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_PRE_DIV_CNT) + 1; in rtc_clk_cpu_freq_get_config()
Drtc_time.c42 int dig_32k_xtal_state = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN); in rtc_clk_cal_internal()
56 rtc_slow_freq_t slow_freq = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); in rtc_clk_cal_internal()
108 return REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_VALUE); in rtc_clk_cal_internal()
/hal_espressif-3.4.0/components/bootloader_support/include/
Desp_flash_encrypt.h52 flash_crypt_cnt = REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_RD_FLASH_CRYPT_CNT); in esp_flash_encryption_enabled()
58 flash_crypt_cnt = REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG, EFUSE_SPI_BOOT_CRYPT_CNT); in esp_flash_encryption_enabled()
/hal_espressif-3.4.0/components/esp_rom/esp32s2/
Dusb_descriptors.c58 const uint32_t mac0 = REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_0_REG, EFUSE_MAC_0); in rom_usb_cdc_set_descriptor_patch()
59 const uint32_t mac1 = REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_1_REG, EFUSE_MAC_1); in rom_usb_cdc_set_descriptor_patch()
/hal_espressif-3.4.0/components/esp_hw_support/port/esp32s3/
Drtc_clk.c157 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); in rtc_clk_slow_freq_get()
178 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); in rtc_clk_fast_freq_get()
366 uint32_t soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL); in rtc_clk_cpu_freq_set_config()
394 uint32_t soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL); in rtc_clk_cpu_freq_get_config()
398 div = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT) + 1; in rtc_clk_cpu_freq_get_config()
Drtc_time.c55 int dig_32k_xtal_state = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN); in rtc_clk_cal_internal()
108 cal_val = REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_VALUE); in rtc_clk_cal_internal()
/hal_espressif-3.4.0/components/esp_gdbstub/esp32c3/
Dgdbstub_esp32c3.c87 while (REG_GET_FIELD(UART_STATUS_REG(UART_NUM), UART_RXFIFO_CNT) == 0) { in esp_gdbstub_getchar()
95 while (REG_GET_FIELD(UART_STATUS_REG(UART_NUM), UART_TXFIFO_CNT) >= 126) { in esp_gdbstub_putchar()
/hal_espressif-3.4.0/components/esp_gdbstub/esp32h2/
Dgdbstub_esp32h2.c86 while (REG_GET_FIELD(UART_STATUS_REG(UART_NUM), UART_RXFIFO_CNT) == 0) { in esp_gdbstub_getchar()
94 while (REG_GET_FIELD(UART_STATUS_REG(UART_NUM), UART_TXFIFO_CNT) >= 126) { in esp_gdbstub_putchar()
/hal_espressif-3.4.0/components/esp_timer/src/
Desp_timer_impl_lac.c136 uint32_t div = REG_GET_FIELD(CONFIG_REG, TIMG_LACT_DIVIDER); in esp_timer_impl_get_counter_reg()
190 if (delta <= 0 && REG_GET_FIELD(INT_ST_REG, TIMG_LACT_INT_ST) == 0) { in esp_timer_impl_set_alarm_id()

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