Searched refs:_U_ (Results 1 – 25 of 784) sorted by relevance
12345678910>>...32
120 #define US_CR_LIN_RSTRX (_U_(0x1) << US_CR_LIN_RSTRX_Pos)121 #define US_CR_LIN_RSTRX_0_Val _U_(0x0) /**< \brief (US_CR_LIN) No effect */122 #define US_CR_LIN_RSTRX_1_Val _U_(0x1) /**< \brief (US_CR_LIN) Resets the receiver */126 #define US_CR_LIN_RSTTX (_U_(0x1) << US_CR_LIN_RSTTX_Pos)127 #define US_CR_LIN_RSTTX_0_Val _U_(0x0) /**< \brief (US_CR_LIN) No effect */128 #define US_CR_LIN_RSTTX_1_Val _U_(0x1) /**< \brief (US_CR_LIN) Resets the transmitter…132 #define US_CR_LIN_RXEN (_U_(0x1) << US_CR_LIN_RXEN_Pos)133 #define US_CR_LIN_RXEN_0_Val _U_(0x0) /**< \brief (US_CR_LIN) No effect */134 #define US_CR_LIN_RXEN_1_Val _U_(0x1) /**< \brief (US_CR_LIN) Enables the receiver, …138 #define US_CR_LIN_RXDIS (_U_(0x1) << US_CR_LIN_RXDIS_Pos)[all …]
85 #define GPIO_GPER_P0 (_U_(0x1) << GPIO_GPER_P0_Pos)87 #define GPIO_GPER_P1 (_U_(0x1) << GPIO_GPER_P1_Pos)89 #define GPIO_GPER_P2 (_U_(0x1) << GPIO_GPER_P2_Pos)91 #define GPIO_GPER_P3 (_U_(0x1) << GPIO_GPER_P3_Pos)93 #define GPIO_GPER_P4 (_U_(0x1) << GPIO_GPER_P4_Pos)95 #define GPIO_GPER_P5 (_U_(0x1) << GPIO_GPER_P5_Pos)97 #define GPIO_GPER_P6 (_U_(0x1) << GPIO_GPER_P6_Pos)99 #define GPIO_GPER_P7 (_U_(0x1) << GPIO_GPER_P7_Pos)101 #define GPIO_GPER_P8 (_U_(0x1) << GPIO_GPER_P8_Pos)103 #define GPIO_GPER_P9 (_U_(0x1) << GPIO_GPER_P9_Pos)[all …]
55 #define TC_CCR_RESETVALUE _U_(0x00000000); /**< \brief (TC_CCR reset_value) Channel Contr…58 #define TC_CCR_CLKEN (_U_(0x1) << TC_CCR_CLKEN_Pos)59 #define TC_CCR_CLKEN_0_Val _U_(0x0) /**< \brief (TC_CCR) No effect. */60 #define TC_CCR_CLKEN_1_Val _U_(0x1) /**< \brief (TC_CCR) Enables the clock if CLKD…64 #define TC_CCR_CLKDIS (_U_(0x1) << TC_CCR_CLKDIS_Pos)65 #define TC_CCR_CLKDIS_0_Val _U_(0x0) /**< \brief (TC_CCR) No effect. */66 #define TC_CCR_CLKDIS_1_Val _U_(0x1) /**< \brief (TC_CCR) Disables the clock. */70 #define TC_CCR_SWTRG (_U_(0x1) << TC_CCR_SWTRG_Pos)71 #define TC_CCR_SWTRG_0_Val _U_(0x0) /**< \brief (TC_CCR) No effect. */72 #define TC_CCR_SWTRG_1_Val _U_(0x1) /**< \brief (TC_CCR) A software trigger is per…[all …]
63 #define USBC_UDCON_RESETVALUE _U_(0x00000100); /**< \brief (USBC_UDCON reset_value) Device Ge…66 #define USBC_UDCON_UADD_Msk (_U_(0x7F) << USBC_UDCON_UADD_Pos)69 #define USBC_UDCON_ADDEN (_U_(0x1) << USBC_UDCON_ADDEN_Pos)71 #define USBC_UDCON_DETACH (_U_(0x1) << USBC_UDCON_DETACH_Pos)73 #define USBC_UDCON_RMWKUP (_U_(0x1) << USBC_UDCON_RMWKUP_Pos)75 #define USBC_UDCON_SPDCONF_Msk (_U_(0x3) << USBC_UDCON_SPDCONF_Pos)78 #define USBC_UDCON_LS (_U_(0x1) << USBC_UDCON_LS_Pos)80 #define USBC_UDCON_TSTJ (_U_(0x1) << USBC_UDCON_TSTJ_Pos)82 #define USBC_UDCON_TSTK (_U_(0x1) << USBC_UDCON_TSTK_Pos)84 #define USBC_UDCON_TSTPCKT (_U_(0x1) << USBC_UDCON_TSTPCKT_Pos)[all …]
68 #define EIC_IER_RESETVALUE _U_(0x00000000); /**< \brief (EIC_IER reset_value) Interrupt En…71 #define EIC_IER_NMI (_U_(0x1) << EIC_IER_NMI_Pos)73 #define EIC_IER_INT1 (_U_(0x1) << EIC_IER_INT1_Pos)74 #define EIC_IER_INT1_0_Val _U_(0x0) /**< \brief (EIC_IER) No effect */75 #define EIC_IER_INT1_1_Val _U_(0x1) /**< \brief (EIC_IER) Enable Interrupt. */79 #define EIC_IER_INT2 (_U_(0x1) << EIC_IER_INT2_Pos)80 #define EIC_IER_INT2_0_Val _U_(0x0) /**< \brief (EIC_IER) No effect */81 #define EIC_IER_INT2_1_Val _U_(0x1) /**< \brief (EIC_IER) Enable Interrupt. */85 #define EIC_IER_INT3 (_U_(0x1) << EIC_IER_INT3_Pos)86 #define EIC_IER_INT3_0_Val _U_(0x0) /**< \brief (EIC_IER) No effect */[all …]
59 #define SPI_CR_RESETVALUE _U_(0x00000000); /**< \brief (SPI_CR reset_value) Control Regis…62 #define SPI_CR_SPIEN (_U_(0x1) << SPI_CR_SPIEN_Pos)63 #define SPI_CR_SPIEN_0_Val _U_(0x0) /**< \brief (SPI_CR) No effect. */64 #define SPI_CR_SPIEN_1_Val _U_(0x1) /**< \brief (SPI_CR) Enables the SPI to transf…68 #define SPI_CR_SPIDIS (_U_(0x1) << SPI_CR_SPIDIS_Pos)69 #define SPI_CR_SPIDIS_0_Val _U_(0x0) /**< \brief (SPI_CR) No effect. */70 #define SPI_CR_SPIDIS_1_Val _U_(0x1) /**< \brief (SPI_CR) Disables the SPI.All pins…74 #define SPI_CR_SWRST (_U_(0x1) << SPI_CR_SWRST_Pos)75 #define SPI_CR_SWRST_0_Val _U_(0x0) /**< \brief (SPI_CR) No effect. */76 #define SPI_CR_SWRST_1_Val _U_(0x1) /**< \brief (SPI_CR) Reset the SPI. A software…[all …]
56 #define SDHC_SSAR_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_SSAR reset_value) SDMA System…60 #define SDHC_SSAR_CMD23_ARG2_Msk (_U_(0xFFFFFFFF) << SDHC_SSAR_CMD23_ARG2_Pos)62 #define SDHC_SSAR_CMD23_MASK _U_(0xFFFFFFFF) /**< \brief (SDHC_SSAR_CMD23) MASK Register */65 #define SDHC_SSAR_ADDR_Msk (_U_(0xFFFFFFFF) << SDHC_SSAR_ADDR_Pos)67 #define SDHC_SSAR_MASK _U_(0xFFFFFFFF) /**< \brief (SDHC_SSAR) MASK Register */83 #define SDHC_BSR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_BSR reset_value) Block Size */86 #define SDHC_BSR_BLOCKSIZE_Msk (_U_(0x3FF) << SDHC_BSR_BLOCKSIZE_Pos)89 #define SDHC_BSR_BOUNDARY_Msk (_U_(0x7) << SDHC_BSR_BOUNDARY_Pos)91 #define SDHC_BSR_BOUNDARY_4K_Val _U_(0x0) /**< \brief (SDHC_BSR) 4k bytes */92 #define SDHC_BSR_BOUNDARY_8K_Val _U_(0x1) /**< \brief (SDHC_BSR) 8k bytes */[all …]
65 #define DMAC_CTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CTRL reset_value) Control */68 #define DMAC_CTRL_SWRST (_U_(0x1) << DMAC_CTRL_SWRST_Pos)70 #define DMAC_CTRL_DMAENABLE (_U_(0x1) << DMAC_CTRL_DMAENABLE_Pos)72 #define DMAC_CTRL_LVLEN0 (_U_(1) << DMAC_CTRL_LVLEN0_Pos)74 #define DMAC_CTRL_LVLEN1 (_U_(1) << DMAC_CTRL_LVLEN1_Pos)76 #define DMAC_CTRL_LVLEN2 (_U_(1) << DMAC_CTRL_LVLEN2_Pos)78 #define DMAC_CTRL_LVLEN3 (_U_(1) << DMAC_CTRL_LVLEN3_Pos)80 #define DMAC_CTRL_LVLEN_Msk (_U_(0xF) << DMAC_CTRL_LVLEN_Pos)82 #define DMAC_CTRL_MASK _U_(0x0F03) /**< \brief (DMAC_CTRL) MASK Register */99 #define DMAC_CRCCTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CRCCTRL reset_value) CRC Control…[all …]
76 #define TCC_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (TCC_CTRLA reset_value) Control A */79 #define TCC_CTRLA_SWRST (_U_(0x1) << TCC_CTRLA_SWRST_Pos)81 #define TCC_CTRLA_ENABLE (_U_(0x1) << TCC_CTRLA_ENABLE_Pos)83 #define TCC_CTRLA_RESOLUTION_Msk (_U_(0x3) << TCC_CTRLA_RESOLUTION_Pos)85 #define TCC_CTRLA_RESOLUTION_NONE_Val _U_(0x0) /**< \brief (TCC_CTRLA) Dithering is disabled …86 #define TCC_CTRLA_RESOLUTION_DITH4_Val _U_(0x1) /**< \brief (TCC_CTRLA) Dithering is done ever…87 #define TCC_CTRLA_RESOLUTION_DITH5_Val _U_(0x2) /**< \brief (TCC_CTRLA) Dithering is done ever…88 #define TCC_CTRLA_RESOLUTION_DITH6_Val _U_(0x3) /**< \brief (TCC_CTRLA) Dithering is done ever…94 #define TCC_CTRLA_PRESCALER_Msk (_U_(0x7) << TCC_CTRLA_PRESCALER_Pos)96 #define TCC_CTRLA_PRESCALER_DIV1_Val _U_(0x0) /**< \brief (TCC_CTRLA) No division */[all …]
56 #define CAN_CREL_RESETVALUE _U_(0x32100000) /**< \brief (CAN_CREL reset_value) Core Release…59 #define CAN_CREL_SUBSTEP_Msk (_U_(0xF) << CAN_CREL_SUBSTEP_Pos)62 #define CAN_CREL_STEP_Msk (_U_(0xF) << CAN_CREL_STEP_Pos)65 #define CAN_CREL_REL_Msk (_U_(0xF) << CAN_CREL_REL_Pos)67 #define CAN_CREL_MASK _U_(0xFFF00000) /**< \brief (CAN_CREL) MASK Register */80 #define CAN_ENDN_RESETVALUE _U_(0x87654321) /**< \brief (CAN_ENDN reset_value) Endian */83 #define CAN_ENDN_ETV_Msk (_U_(0xFFFFFFFF) << CAN_ENDN_ETV_Pos)85 #define CAN_ENDN_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_ENDN) MASK Register */99 #define CAN_MRCFG_RESETVALUE _U_(0x00000002) /**< \brief (CAN_MRCFG reset_value) Message RAM…102 #define CAN_MRCFG_QOS_Msk (_U_(0x3) << CAN_MRCFG_QOS_Pos)[all …]
62 #define RTC_MODE0_CTRLA_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE0_CTRLA reset_value) MODE0 Co…65 #define RTC_MODE0_CTRLA_SWRST (_U_(0x1) << RTC_MODE0_CTRLA_SWRST_Pos)67 #define RTC_MODE0_CTRLA_ENABLE (_U_(0x1) << RTC_MODE0_CTRLA_ENABLE_Pos)69 #define RTC_MODE0_CTRLA_MODE_Msk (_U_(0x3) << RTC_MODE0_CTRLA_MODE_Pos)71 #define RTC_MODE0_CTRLA_MODE_COUNT32_Val _U_(0x0) /**< \brief (RTC_MODE0_CTRLA) Mode 0: 32-bit …72 #define RTC_MODE0_CTRLA_MODE_COUNT16_Val _U_(0x1) /**< \brief (RTC_MODE0_CTRLA) Mode 1: 16-bit …73 #define RTC_MODE0_CTRLA_MODE_CLOCK_Val _U_(0x2) /**< \brief (RTC_MODE0_CTRLA) Mode 2: Clock/Ca…78 #define RTC_MODE0_CTRLA_MATCHCLR (_U_(0x1) << RTC_MODE0_CTRLA_MATCHCLR_Pos)80 #define RTC_MODE0_CTRLA_PRESCALER_Msk (_U_(0xF) << RTC_MODE0_CTRLA_PRESCALER_Pos)82 #define RTC_MODE0_CTRLA_PRESCALER_OFF_Val _U_(0x0) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = …[all …]
55 #define EIC_CTRL_RESETVALUE _U_(0x00) /**< \brief (EIC_CTRL reset_value) Control */58 #define EIC_CTRL_SWRST (_U_(0x1) << EIC_CTRL_SWRST_Pos)60 #define EIC_CTRL_ENABLE (_U_(0x1) << EIC_CTRL_ENABLE_Pos)61 #define EIC_CTRL_MASK _U_(0x03) /**< \brief (EIC_CTRL) MASK Register */75 #define EIC_STATUS_RESETVALUE _U_(0x00) /**< \brief (EIC_STATUS reset_value) Status */78 #define EIC_STATUS_SYNCBUSY (_U_(0x1) << EIC_STATUS_SYNCBUSY_Pos)79 #define EIC_STATUS_MASK _U_(0x80) /**< \brief (EIC_STATUS) MASK Register */94 #define EIC_NMICTRL_RESETVALUE _U_(0x00) /**< \brief (EIC_NMICTRL reset_value) Non-Maskable…97 #define EIC_NMICTRL_NMISENSE_Msk (_U_(0x7) << EIC_NMICTRL_NMISENSE_Pos)99 #define EIC_NMICTRL_NMISENSE_NONE_Val _U_(0x0) /**< \brief (EIC_NMICTRL) No detection */[all …]
