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Searched refs:TC4 (Results 1 – 25 of 109) sorted by relevance

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/hal_atmel-latest/asf/sam0/include/samd20/
Dsamd20e14.h366 #define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ macro
450 #define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ macro
453 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
Dsamd20e15.h366 #define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ macro
450 #define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ macro
453 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
Dsamd20e16.h366 #define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ macro
450 #define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ macro
453 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
Dsamd20e17.h366 #define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ macro
450 #define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ macro
453 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
Dsamd20e18.h366 #define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ macro
450 #define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ macro
453 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
Dsamd20g14.h376 #define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ macro
462 #define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ macro
465 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
Dsamd20g15.h376 #define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ macro
462 #define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ macro
465 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
Dsamd20g16.h376 #define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ macro
462 #define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ macro
465 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
Dsamd20g17.h376 #define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ macro
462 #define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ macro
465 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
Dsamd20g17u.h376 #define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ macro
462 #define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ macro
465 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
Dsamd20g18.h376 #define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ macro
462 #define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ macro
465 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
Dsamd20g18u.h376 #define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ macro
462 #define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ macro
465 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
Dsamd20j14.h384 #define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ macro
472 #define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ macro
477 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances Lis…
Dsamd20j15.h384 #define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ macro
472 #define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ macro
477 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances Lis…
Dsamd20j16.h384 #define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ macro
472 #define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ macro
477 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances Lis…
Dsamd20j17.h384 #define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ macro
472 #define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ macro
477 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances Lis…
Dsamd20j18.h384 #define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ macro
472 #define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ macro
477 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances Lis…
/hal_atmel-latest/asf/sam0/include/samd21/
Dsamd21e15a.h392 #define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ macro
493 #define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ macro
496 #define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
Dsamd21e16a.h392 #define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ macro
493 #define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ macro
496 #define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
Dsamd21e17a.h392 #define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ macro
493 #define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ macro
496 #define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
Dsamd21e18a.h392 #define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ macro
493 #define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ macro
496 #define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
Dsamd21j15a.h410 #define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ macro
515 #define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ macro
520 #define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
Dsamd21j16a.h410 #define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ macro
515 #define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ macro
520 #define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
Dsamd21j17a.h410 #define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ macro
515 #define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ macro
520 #define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
Dsamd21j18a.h410 #define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ macro
515 #define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ macro
520 #define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */

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