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Searched refs:TC1 (Results 1 – 25 of 160) sorted by relevance

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/hal_atmel-latest/asf/sam0/include/samd20/
Dsamd20e14.h363 #define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ macro
447 #define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ macro
453 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
Dsamd20e15.h363 #define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ macro
447 #define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ macro
453 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
Dsamd20e16.h363 #define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ macro
447 #define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ macro
453 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
Dsamd20e17.h363 #define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ macro
447 #define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ macro
453 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
Dsamd20e18.h363 #define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ macro
447 #define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ macro
453 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
Dsamd20g14.h373 #define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ macro
459 #define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ macro
465 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
Dsamd20g15.h373 #define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ macro
459 #define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ macro
465 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
Dsamd20g16.h373 #define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ macro
459 #define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ macro
465 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
Dsamd20g17.h373 #define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ macro
459 #define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ macro
465 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
Dsamd20g17u.h373 #define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ macro
459 #define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ macro
465 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
Dsamd20g18.h373 #define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ macro
459 #define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ macro
465 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
Dsamd20g18u.h373 #define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ macro
459 #define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ macro
465 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
Dsamd20j14.h381 #define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ macro
469 #define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ macro
477 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances Lis…
Dsamd20j15.h381 #define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ macro
469 #define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ macro
477 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances Lis…
Dsamd20j16.h381 #define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ macro
469 #define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ macro
477 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances Lis…
Dsamd20j17.h381 #define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ macro
469 #define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ macro
477 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances Lis…
Dsamd20j18.h381 #define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ macro
469 #define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ macro
477 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances Lis…
/hal_atmel-latest/asf/sam0/include/samc20/
Dsamc20e16a.h408 #define TC1 (0x42003400) /**< \brief (TC1) APB Base Address */ macro
527 #define TC1 ((Tc *)0x42003400UL) /**< \brief (TC1) APB Base Address */ macro
532 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */
Dsamc20e17a.h408 #define TC1 (0x42003400) /**< \brief (TC1) APB Base Address */ macro
527 #define TC1 ((Tc *)0x42003400UL) /**< \brief (TC1) APB Base Address */ macro
532 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */
Dsamc20g16a.h408 #define TC1 (0x42003400) /**< \brief (TC1) APB Base Address */ macro
527 #define TC1 ((Tc *)0x42003400UL) /**< \brief (TC1) APB Base Address */ macro
532 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */
Dsamc20g17a.h408 #define TC1 (0x42003400) /**< \brief (TC1) APB Base Address */ macro
527 #define TC1 ((Tc *)0x42003400UL) /**< \brief (TC1) APB Base Address */ macro
532 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */
Dsamc20g18a.h408 #define TC1 (0x42003400) /**< \brief (TC1) APB Base Address */ macro
527 #define TC1 ((Tc *)0x42003400UL) /**< \brief (TC1) APB Base Address */ macro
532 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */
Dsamc20j15a.h408 #define TC1 (0x42003400) /**< \brief (TC1) APB Base Address */ macro
527 #define TC1 ((Tc *)0x42003400UL) /**< \brief (TC1) APB Base Address */ macro
532 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */
Dsamc20e15a.h408 #define TC1 (0x42003400) /**< \brief (TC1) APB Base Address */ macro
527 #define TC1 ((Tc *)0x42003400UL) /**< \brief (TC1) APB Base Address */ macro
532 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */
Dsamc20e18a.h408 #define TC1 (0x42003400) /**< \brief (TC1) APB Base Address */ macro
527 #define TC1 ((Tc *)0x42003400UL) /**< \brief (TC1) APB Base Address */ macro
532 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */

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