Searched refs:REG_XDMAC_CSUS5 (Results 1 – 4 of 4) sorted by relevance
119 #define REG_XDMAC_CSUS5 (0x400781C0) /**< (XDMAC) Channel Source Microblock Stride (chid = … macro476 #define REG_XDMAC_CSUS5 (*(__IO uint32_t*)0x400781C0U) /**< (XDMAC) Channel Source Microblo… macro
119 #define REG_XDMAC_CSUS5 (0x400781C0) /**< (XDMAC) Channel Source Microblock Stride 5 */ macro475 #define REG_XDMAC_CSUS5 (*(__IO uint32_t*)0x400781C0U) /**< (XDMAC) Channel Source Microblo… macro
119 #define REG_XDMAC_CSUS5 (0x400781C0) /**< (XDMAC) Channel Source Microblock Stride (chid = … macro475 #define REG_XDMAC_CSUS5 (*(__IO uint32_t*)0x400781C0U) /**< (XDMAC) Channel Source Microblo… macro
