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Searched refs:REG_XDMAC_CSA5 (Results 1 – 4 of 4) sorted by relevance

/hal_atmel-latest/asf/sam/include/samv71/instance/
Dxdmac.h111 #define REG_XDMAC_CSA5 (0x400781A0) /**< (XDMAC) Channel Source Address Register (chid = 0… macro
468 #define REG_XDMAC_CSA5 (*(__IO uint32_t*)0x400781A0U) /**< (XDMAC) Channel Source Address … macro
/hal_atmel-latest/asf/sam/include/same70b/instance/
Dxdmac.h111 #define REG_XDMAC_CSA5 (0x400781A0) /**< (XDMAC) Channel Source Address Register 5 */ macro
467 #define REG_XDMAC_CSA5 (*(__IO uint32_t*)0x400781A0U) /**< (XDMAC) Channel Source Address … macro
/hal_atmel-latest/asf/sam/include/same70/instance/
Dxdmac.h111 #define REG_XDMAC_CSA5 (0x400781A0) /**< (XDMAC) Channel Source Address Register (chid = 0… macro
467 #define REG_XDMAC_CSA5 (*(__IO uint32_t*)0x400781A0U) /**< (XDMAC) Channel Source Address … macro
/hal_atmel-latest/asf/sam/include/samv71b/instance/
Dxdmac.h111 #define REG_XDMAC_CSA5 (0x400781A0) /**< (XDMAC) Channel Source Address Register 5 */ macro
467 #define REG_XDMAC_CSA5 (*(__IO uint32_t*)0x400781A0U) /**< (XDMAC) Channel Source Address … macro